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a semiconductor device

A semiconductor and polycrystalline semiconductor technology, applied in the direction of semiconductor devices, electric solid state devices, electrical components, etc., which can solve the problems of inability to possess, high local temperature of NBL, and inability to set larger lateral dimensions.

Active Publication Date: 2020-10-27
NANJING SILERGY SEMICON TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to make the capacitance of the ESD semiconductor device lower, the lateral size of the P+ region cannot be set larger
However, in the semiconductor device in which the above-mentioned low-capacitance diode and the clamping diode are stacked, the current discharge path of the ESD semiconductor device is P+→Nepi→NBL→P-sub, then when the size of the P+ region is small, as figure 1 As shown, most of the current discharged through the ESD device flows through some areas of the NBL, which may cause the local temperature of the NBL to be too high and damage the device
Obviously, figure 1 The ESD device shown cannot have high robust performance while having low capacitance

Method used

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Experimental program
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Embodiment 1

[0059] The semiconductor device of Embodiment 1 mainly includes a first diode D1, and the first diode D1 is located on the semiconductor substrate N-Sub, which mainly includes a first region located on the N-type doped semiconductor substrate N-Sub The upper first intrinsic polycrystalline semiconductor region I-Ploy, the first doped region N+1 with N-type doping in the first intrinsic polycrystalline semiconductor region I-Ploy, and the first intrinsic polycrystalline semiconductor region N+1 located in the first intrinsic polycrystalline semiconductor region I-Ploy The region I-Ploy has a second doped region P+1 with P-type doping. In the first embodiment, the first doped region N+1 is the cathode contact region of the first diode D1, and the second doped region P+1 is the anode contact region of the first diode D1. The impurity region N+1 and the second doped region P+1 are laterally arranged on the surface of the first intrinsic polycrystalline semiconductor region I-Ploy,...

Embodiment 2

[0066] The difference between the second embodiment and the first embodiment is that when the fifth doped region P+2 is electrically connected to the substrate N-Sub through a conductive channel, the specific structure of the conductive channel is different, and the rest are the same. In the second embodiment, the conductive channel includes a sixth doped region N+3 that is on the same plane as the fifth doped region P+2 and has N-type doping, and is extended from the sixth doped region N+3 To the polycrystalline column N-Ploy in the third region in the semiconductor substrate N-Sub, the doping type of the polycrystalline column N-Ploy is N type. The fifth doped region P+2 is first electrically connected to the sixth doped region N+3 through the third electrode M3, and then electrically connected to the semiconductor substrate N-Sub through the polycrystalline column N-Ploy. Because when the first intrinsic polycrystalline semiconductor region I-Ploy is formed, a third intrins...

Embodiment 3

[0068] The third embodiment is different from the first embodiment in that when the fifth doped region P+2 is electrically connected to the substrate N-Sub through a conductive channel, the specific structure of the conductive channel is different, and the third electrode The structure is different, and the rest are the same. In the third embodiment, the conductive channel includes a second buried layer NBL with N-type doping on the third region of the semiconductor substrate N-Sub, and the third electrode M3 is located by the fifth doped region P+2 The surface of the semiconductor substrate N-Sub extends to the second buried layer NBL to form an ohmic contact with the second buried layer NBL.

[0069] Figure 5 It is a schematic structural diagram of a semiconductor device according to Embodiment 4 of the present invention. The equivalent circuit diagram corresponding to the semiconductor device in Embodiment 4 is also as Figure 11 shown.

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Abstract

The present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate and at least one first diode on the semiconductor substrate; the first diode includesa first intrinsic polycrystalline semiconductor region above on the first portion of the substrate, a first doped region which has a first doping type and is located in the first intrinsic polycrystalline semiconductor region, and a second doped region which has a second doping type and is located in the first intrinsic polycrystalline semiconductor region. Since the first diode is composed of the two doped regions which are laterally arranged, have different doping types and are located in the intrinsic polycrystalline semiconductor region, the semiconductor device has ultra-low parasitic capacitance; the first diode can be laterally arranged on the semiconductor substrate together with a clamp structure, and therefore, the lateral dimension of a third doped region above a first buried layer can be the same as the lateral dimension of the first buried layer, and the robustness of the semiconductor device can be improved.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same, more particularly to a semiconductor device with low capacitance and high robustness. Background technique [0002] In ESD devices, avalanche breakdown diodes or Zener diodes are usually used as clamping devices. However, when traditional avalanche breakdown diodes and Zener diodes are used in the low-voltage range, there will be large leakage current and capacitance, so in the current In the prior art, in order to make the ESD device have a lower trigger voltage and leakage current, a diode with a lower capacitance is usually used in series with the clamping device. [0003] like figure 1 As shown, it is a schematic diagram of a cross-sectional structure of an ESD semiconductor device realized in the prior art, wherein the P-type semiconductor substrate P-sub and the NBL buried layer form a clamping diode, such as a Zener diode, and Nepi and the P+ region ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
CPCH01L27/0255
Inventor 殷登平王世军姚飞赵豹童亮
Owner NANJING SILERGY SEMICON TECH CO LTD