A board-level package design optimization method for integrated qfn chips

Abstract

The invention discloses a board-level packaging design optimization method for integrated QFN chips, the steps include: determining the parameters of the integrated circuit board and establishing a thermal coupling simulation model; constructing the performance function of the thermal stress of the pad and the warpage of the chip; constructing the thermal stress of the pad Limit state equations of stress and wafer warpage; construct approximate limit state equations of pad thermal stress and wafer warpage; check pad strength and wafer warpage; end and output the optimal design of board-level packaging and the optimal error of fixed points tolerance. The present invention builds a thermal-mechanical coupling simulation model for the board-level packaging of the integrated QFN chip, and uses interval analysis technology to establish the limit state equation. The optimal design scheme of the obtained board-level packaging can not only meet the design requirements of thermal stress and warpage, but also has The lowest processing cost and process difficulty. Moreover, the method proposed in the present invention has good comprehensive performance in terms of efficiency and convergence.

Description

technical field [0001] The invention belongs to the field of integrated circuit packaging design, and in particular relates to a board-level packaging design optimization method for integrated QFN chips. Background technique [0002] Packaging can not only provide the necessary electrical connection between integrated circuits and external systems, but also provide mechanical or environmental protection for integrated circuits. With the rapid development of microelectronics technology, high-level packaging design has become a challenging task. Packaging can generally be defined into four levels: wafer level, chip level, board level and system level. Board-level packaging refers to the joint installation of chips and passive components on a printed circuit board to form an integrated circuit board with specific functions. Board-level packaging needs to provide a stable and reliable working environment for the integrated chip; therefore, the packaging characteristics of the ...

AI Technical Summary

Problems solved by technology

First of all, building an effective optimization model not only needs to comprehensively consider the electrical properties, thermal properties and mechanical properties of the integrated circuit board, but also needs to take into account the manufacturing cost and process difficulty, which is very challenging for ordinary technicians

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