Module substrate

A module substrate and metal wiring technology, applied in the field of module substrates, can solve problems such as insufficiency

Inactive Publication Date: 2018-10-09
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, in Patent Document 1, it is not sufficient to radiate signals in the frequency band of 100 GHz or higher into space or to collect power in space.

Method used

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Embodiment approach 1

[0071] Figure 4 It is a plan view showing an example of the module substrate 10 according to Embodiment 1 of the present invention. Figure 5A yes Figure 4 Sectional view of A1-A2. Figure 5B yes Figure 4 Sectional view of B1-B2. Figure 5C yes Figure 4 Sectional view of C1-C2.

[0072] The module substrate 10 has four metal wiring layers (wiring layer 11 a to wiring layer 11 d ), and a dielectric layer 12 between these wiring layers. The module substrate 10 is formed as a laminated substrate by, for example, a build-up method. Four metal wiring layers (wiring layer 11 a to wiring layer 11 d ) are laminated via dielectric layer 12 .

[0073] The wiring layer 11 a is a surface layer of the module substrate 10 and has a transmission line 13 , a coupling element 14 , a ground conductor plane 15 and an alignment mark 18 .

[0074] The transmission line 13 is formed on the wiring layer 11a, and is connected to the high-frequency terminal 2a of the CMOS chip 2 (refer to ...

Embodiment approach 2

[0099] Figure 9 It is a plan view showing an example of the module substrate 20 according to Embodiment 2 of the present invention. Figure 10A yes Figure 9 Sectional view of A1-A2. Figure 10B yes Figure 9 Sectional view of B1-B2. Figure 10C yes Figure 9 Sectional view of C1-C2. In addition, in Figure 9 , Figure 10A ~ Figure 10C in, for with Figure 4 , Figure 5A ~ Figure 5C The same configurations are assigned the same symbols and descriptions thereof are omitted.

[0100] The module substrate 20 differs from the module substrate 10 in that a wiring layer 21 a is a surface layer and that a via structure 26 is provided between the wiring layer 21 a and the wiring layer 11 b.

[0101] The wiring layer 21 a is a surface layer of the module substrate 20 and has the transmission line 13 , the coupling element 14 , the ground conductor plane 25 and the alignment mark 28 .

[0102] The transmission line 13 is formed on the wiring layer 21a, and is connected to th...

Embodiment approach 3

[0114] Figure 12 It is a plan view showing an example of the module substrate 30 according to Embodiment 3 of the present invention. Figure 13A yes Figure 12 Sectional view of A1-A2. Figure 13B yes Figure 12 Sectional view of B1-B2. Figure 13C yes Figure 12 Sectional view of C1-C2. In addition, in Figure 12 , Figure 13A ~ Figure 13C in, for with Figure 9 , Figure 10A ~ Figure 10C The same configurations are assigned the same symbols and descriptions thereof are omitted.

[0115] In the module substrate 30 , the wiring layer 21 a serving as the surface layer of the module substrate 20 is replaced with a wiring layer 31 a and a wiring layer 31 e. Furthermore, a via structure 36 connecting the wiring layer 31a and the wiring layer 31e is added.

[0116] The wiring layer 31 a has transmission lines 13 and coupling elements 14 .

[0117] The transmission line 13 is formed on the wiring layer 31a, and is connected to the high-frequency terminal 2a of the CMOS ...

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Abstract

A module substrate includes a surface layer to which a rectangular waveguide structure having a waveguide aperture is to be connected; metal layers stacked with a dielectric layer between each pair thereof and including a first metal layer that includes a transmission line and a coupling element at a portion of the transmission line and a second metal layer positioned further than the first metallayer from the rectangular waveguide structure; and vias connecting the adjacent metal layers. The surface layer has a first opening facing the waveguide aperture. The first opening surrounds the coupling element in plan view from the surface layer. A dielectric layer region surrounded by some of the vias is formed within a projection area of the first opening between the first and second metal layers. The region has a size smaller than the waveguide aperture in the plan view.

Description

technical field [0001] The present invention relates to module substrates. In detail, the invention relates to a module substrate realizing a combination of a waveguide and an integrated circuit as an antenna element. Background technique [0002] In recent years, high-speed wireless communication systems using frequencies of 100 GHz or higher and high-resolution radar systems have been studied because broadband signals can be used. For example, attempts have been made to integrate front-end circuits for high-speed wireless communication systems using the 300 GHz band, and high-resolution radar systems using the 140 GHz band. [0003] In existing wireless communication systems or radar systems, in order to radiate high-frequency signals (wireless signals) into space or collect power in space, when connecting integrated circuits and antenna elements, coupling with antenna elements is considered. [0004] For example, in Patent Document 1, the connection between an integrate...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01P5/107
CPCH01P5/107H01L2223/6677H01L23/66H01L23/49822H01L23/49838H01L2223/6627H01L24/16H01L2224/16227H01L2224/16265H01P3/121H01L2224/16225
Inventor 水野纮一
Owner PANASONIC CORP
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