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The method of fabricating the son device

A device, dry etching technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as complex manufacturing processes and changes in transistor manufacturing processes

Active Publication Date: 2020-12-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a kind of preparation method of SON device, to solve the manufacturing process of SON device usually more complicated at present, the problem that the existing transistor manufacturing process needs to be changed to a great extent

Method used

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  • The method of fabricating the son device
  • The method of fabricating the son device
  • The method of fabricating the son device

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Embodiment Construction

[0046] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0047] In the following description, it will be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being 'under' another layer, it can be directly under, and / or one or more intervening layers may also be present. In addition, designations regarding 'on...

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Abstract

The invention provides a preparation method of a SON device. The preparation method comprises a substrate, forming a transition layer on the substrate, forming a first dielectric layer and a semiconductor layer arranged at intervals on the transition layer, and forming a mask layer on the first dielectric layer and the semiconductor layer; performing the first etching to form a first opening to expose the first group side of the transition layer; performing the second etching so as to partially etch the transition layer under the semiconductor layer; performing the third etching to form a second opening to expose the second group side of the transition layer; performing the fourth etching so as to completely remove the transition layer under the semiconductor layer; and forming a hole layer under the semiconductor layer. The transition layer under the semiconductor is etched at twice through the method provided by the invention, twice etching on the transition layer is realized throughthe formed first opening and second opening, thereby forming the SON device structure; and the hole layer under the semiconductor layer can be simply and effectively formed, thereby better finishingthe preparation of the device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a SON device. Background technique [0002] In order to improve the performance and performance-price ratio of integrated circuit chips, it is a main way to reduce the feature size of the device to increase the integration level. However, as the size of the device shrinks, power consumption and leakage current become the most concerned issues. Silicon-On-Insulator SOI (Silicon-On-Insulator) structure has become the preferred structure of deep submicron MOS devices because it can well suppress the short channel effect and improve the ability of devices to be scaled down. [0003] With the continuous development of SOI technology, researchers have developed a new type of transistor structure - SON (Silicon on nothing) transistor. SON (Silicon-On-Nothing) is an advanced technology developed by CEA-LETI and ST STMicroelectronics for sub-90nm CMOS. S...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
CPCH01L21/76283
Inventor 刘张李莘海维蒙飞孙玉红
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP