A test method and test system for a full model of a standard cell library

Abstract

The invention provides a method for testing the full model of a standard cell library, comprising the following steps: step 201, performing multiple physical rule checks on the standard cell layout; step 202: performing formal verification of the standard cell library model; step 203, performing standard cell Benchmark electrical characteristic verification of the library; step 204 , performing chip design silicon verification of the standard cell library. The invention also provides a test system for the full model of the standard unit library. The invention can complete the test and verification of the full model of the standard unit library quickly and with high coverage.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to the field of integrated circuit design automation, and specifically relates to a test method and a test system for a full model of a standard cell library. Background technique [0002] The standard cell library is a collection of basic logic cells developed based on a mature and stable process. Each standard cell library has hundreds to thousands of cells, and the cell types are very rich, including basic cells, combinational logic cells, sequential logic cells, and special cells. The standard cell library is the basic database for VLSI (Very Large Scale Integration) automatic design. Its database model is rich, including cell simulation library, cell symbol, cell layout, logic function model, timing synthesis library model, and cell netlist. , layout and routing library and other data. Such as figure 1 As shown, a full set of standard cell library models supports the...

AI Technical Summary

Problems solved by technology

The disadvantages of adopting this method are as follows: 1. The physical design rule check of the standard cells is completed one by one, but the standard cells in the actual chip are randomly spliced ​​together, and the existing verification method is not perfect in the verification of the cell splicing.

2. Design process verification can ensure the correctness of various library model data formats, but cannot guarantee the consistency between various library model data

3. A single chip design cannot guarantee the electrical characteristics of the standard cell library

After the standard cell library with incomplete verification is released, potential library model data errors or information differences between models will directly affect the application of chip designers, and even lead to chip tape-out failures

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