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Method of detecting alignment shift

A test area and control gate technology, which is used in semiconductor/solid-state device testing/measurement, semiconductor devices, electrical components, etc., and can solve problems such as the inability to effectively detect the floating gate and control gate offset of flash memory cells.

Active Publication Date: 2020-06-16
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a method for detecting alignment offset, so as to solve the problem that the existing technology cannot effectively detect whether there is an offset between the floating gate and the control gate of the flash memory unit.

Method used

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Embodiment Construction

[0035] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0036] refer to figure 1 , which is a flowchart of a method for detecting an alignment offset provided in an embodiment, and the method for detecting an alignment offset includes:

[0037] S1: Provide a substrate, the substrate includes a flash memory area and a test area, the flash memory area is used to form flash memory cells, an isolation structure is formed in the substrate corresponding to the test area, and a control gate is formed on the isolation structure polysilicon layer;

[0038] S2: Etching part ...

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Abstract

The invention provides a method for detecting alignment deviation, comprising forming a control gate polysilicon layer on the isolation structure in the substrate of the wafer test area, and then forming a dielectric layer on the control gate polysilicon layer, and forming a dielectric layer on the dielectric layer Form two openings with different cross-sectional widths, wherein the two openings cover the control gate polysilicon layer with a smaller cross-sectional width, and finally remove the control gate polysilicon layer below the dielectric layer to form the first control grid and the second control grid, the cross-sectional widths of the first control grid and the second control grid are not equal, the length and material of the first control grid and the second control grid are all the same, and the ratio of their resistances is inversely proportional to the section width. By detecting the resistance of the first control grid and the second control grid, it can effectively reflect the floating gate of the flash memory unit and the control Check whether the grid has shifted, and improve the online monitoring ability of the product.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for detecting alignment deviation. Background technique [0002] With the rapid development of portable electronic devices, the requirements for data storage are getting higher and higher. Semiconductor memory for storing data is classified into volatile memory and nonvolatile memory. Among non-volatile memories, flash memory (flash memory) has become an extremely important device due to its high chip storage density and better process adaptability. [0003] When self-alignment technology is used to form flash memory cells, the exposure process is often used. Due to the alignment deviation between different wafers or two-layer exposures at different positions of a single wafer in the exposure process, the exposure of the floating gate is relative to the control gate. Exposure will inevitably produce alignment shift, and the ordinary exposure process is limite...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66H01L27/11519H01L27/11521H10B41/10H10B41/30
CPCH01L22/12H01L22/14H10B41/10H10B41/30
Inventor 曹子贵
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP