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Transistor structure adopting embedded bit line and manufacturing method of transistor structure

A technology of embedded bit lines and manufacturing methods, which is applied in the direction of transistors, semiconductor/solid-state device manufacturing, and electric solid-state devices. It can solve the problems of reduced node contact area and device performance degradation, and achieves reduced channel leakage and increased area. Effect

Pending Publication Date: 2018-11-23
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a transistor structure using buried bit lines and a manufacturing method thereof, which is used to solve the problem of reducing the contact area of ​​nodes due to the high integration of devices in the prior art. , leading to the problem of degraded device performance

Method used

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  • Transistor structure adopting embedded bit line and manufacturing method of transistor structure
  • Transistor structure adopting embedded bit line and manufacturing method of transistor structure
  • Transistor structure adopting embedded bit line and manufacturing method of transistor structure

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Embodiment 1

[0112]The invention provides a method for manufacturing a transistor structure using a buried bit line, comprising the following steps:

[0113] See first Figure 8 , performing step S1: providing a substrate 201 in which an isolation structure 202 is disposed, and the isolation structure defines a plurality of active regions 203 in the substrate.

[0114] Specifically, the substrate 201 includes but not limited to Si, Ge, SiGe, SOI and other semiconductor substrates. The isolation structure 202 may be a shallow trench isolation (Shallow Trench Isolation, STI for short).

[0115] As an example, see Figure 4 , shown as a top view of a single active region 203 in the substrate, where the substrate is at Figure 4 The cross-sectional view of plane A1 is shown as Figure 5 As shown, the substrate is in Figure 4 The cross-sectional view of plane A2 is shown as Figure 6 As shown, the substrate is in Figure 4 The cross-sectional view of the A3 plane is shown as Figure 7 ...

Embodiment 2

[0145] The present invention also provides a transistor structure using a buried bit line, including a substrate, an isolation structure, a drain sinking groove, a first word line trench, a second word line trench, a buried word line and A buried bit line, wherein the isolation structure defines a plurality of active regions in the substrate, and the drain sinking groove is formed in the active regions.

[0146] see Figure 19 , shown as a single active region 203, drain sinking groove 204, first word line trench 206, second word line trench 207, buried word line 208a, buried word line 208b, From the planar layout of the bit line trench 209 and the buried bit line 210 , it can be seen that the drain sinking groove 204 overlaps the middle section of the active region 203 .

[0147] Please refer to Figure 23, which shows the transistor structure for the Figure 19 As shown in the cross-sectional view of the B1 plane, it can be seen that the first word line trench 206 and the s...

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Abstract

The invention provides a transistor structure adopting an embedded bit line and a manufacturing method of the transistor structure. The transistor structure comprises a substrate, an isolation structure, a drain electrode sinking groove, a first word line trench, a second word line trench, an embedded type word line, a bit line trench and an embedded type bit line. According to the manufacturing method, the structure of the transistor is changed by forming the drain electrode sinking groove, so that the transistor is provided with the embedded bit line; and by virtue of the drain electrode sinking groove formed in the transistor, the node contact area of the source electrode and the drain electrode is increased, the etching of the word lines is facilitated, and the leakage of the channelsis reduced. The transistor structure adopting the embedded bit line can be applied to active areas with different shapes, and can be applied to different electric circuits.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuits, and relates to a transistor structure using buried bit lines and a manufacturing method thereof. Background technique [0002] Semiconductor memory (semi-conductor memory) is a memory that uses semiconductor circuits as storage media. The internal memory is composed of semiconductor integrated circuits called memory chips. Semiconductor memory can be divided into random access memory (RAM for short) and read-only memory (read-only ROM) according to its function. It has the advantages of small size, fast storage speed, high storage density, and easy interface with logic circuits. RAM includes DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and when the power is turned off or the power is turned off, the information in it will be lost. DRAM is mainly used for main memory (the main part of memory), and SRAM is mainly used for cache memory. ROM is mainly...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242H10B12/00
CPCH10B12/053H10B12/00H10B12/488H10B12/482
Inventor 赵亮
Owner CHANGXIN MEMORY TECH INC
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