Three-dimensional memory, mos field effect transistor and manufacturing method thereof

Abstract

The invention provides a three-dimensional memory, an MOS field effect transistor and a manufacturing method thereof. The transistor comprises a semiconductor substrate, a gate insulating layer and agate electrode, wherein the gate insulating layer is located on the semiconductor substrate; the gate electrode is located on the gate insulating layer, and the gate electrode comprises a trapping layer located on the gate insulating layer, wherein the trapping layer comprises a carbon silicon compound or a carbon germanium silicon compound. The invention provides the MOS field effect transistor and the manufacturing method thereof; the trapping layer is added to one side, close to the gate insulating layer, of a blocking layer, and the material of the trapping layer is the carbon silicon compound or the carbon germanium silicon compound, so that the concentration of boron in the trapping layer in the steady state is greater than that of boron in the blocking layer and a metal silicide layer; and in addition, the difference between the concentration of boron in the blocking layer and the concentration of boron in the metal silicide layer is reduced, so that the boron segregation coefficient is effectively lowered and the problem of depletion of the gate electrode can be further solved.

Description

technical field [0001] The invention mainly relates to the field of semiconductor manufacturing, in particular to a three-dimensional memory, a MOS field effect transistor and a manufacturing method thereof. Background technique [0002] In order to overcome the limitations of two-dimensional memory devices, the industry has developed memory devices with a three-dimensional (3D) structure to increase integration density by three-dimensionally arranging memory cells on a substrate. [0003] In a three-dimensional memory device such as a 3D NAND flash memory, the three-dimensional memory device may include a memory array and peripheral circuits. A memory array may include a core area and a stair area. The step region is used to lead out the contact portion for the gate layer in each layer of the memory array. These gate layers are used as word lines of the memory array to perform operations such as programming, erasing, and reading. The peripheral circuit implements functio...

AI Technical Summary

Problems solved by technology

During doping steps such as boron doping, the boron segregation coefficient between the metal compound and the barrier layer is very large, which leads to severe gate depletion in PMOS FETs

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