A stacked SRAM array structure with high energy efficiency and low power consumption
A technology of array structure and utilization rate, which is applied in the field of stacked SRAM array structure, can solve the problems of high conduction loss energy utilization efficiency of converters, low voltage conversion ratio, etc., and achieve the goals of easy implementation, avoiding design, and avoiding voltage loss Effect
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[0033] Suppose the battery voltage of the stacked SRAM is 1.8V, the write enable signal is a square wave signal with a frequency of 10kHz, and the global clock signal is a square wave signal with a frequency of 20kHz. Stable at 1.8V, 1.35V, 0.9V, and 0.45V. At the same time, in the case of a voltage range of 450mV, the write / read power consumption of an SRAM cell is only 2.45pJ / acc and 2.18pJ / acc for each access, and the highest output power consumption is only 60μW. The deviation of power consumption is within 10%, and the efficiency in the worst case is as high as 94%, so as to achieve the purpose of low power consumption and high energy conversion efficiency.
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