A stacked SRAM array structure with high energy efficiency and low power consumption

A technology of array structure and utilization rate, which is applied in the field of stacked SRAM array structure, can solve the problems of high conduction loss energy utilization efficiency of converters, low voltage conversion ratio, etc., and achieve the goals of easy implementation, avoiding design, and avoiding voltage loss Effect

Active Publication Date: 2018-12-07
XI AN JIAOTONG UNIV
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AI-Extracted Technical Summary

Problems solved by technology

In the method of reducing the power supply voltage, a linear regulator or a step-down DC converter can be used, but the voltage conversion ratio (that is, the ratio of the output volt...
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Method used

[0026] The MOS transistor adopts a deep N-well process, the main purpose is to eliminate its lining bias effect, and the operating voltage of the sense amplifier 5 is VDD, so as to avoid writing and reading errors due to low voltage limitations.
[0029] 2) SRAM array 4, the SRAM unit is an 8-tube SRAM unit, and the SRAM unit is composed of a cross-coupled inverter, a write access device and a read path. Since the cell node is separated from the read ...
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Abstract

The invention discloses a stacked SRAM array structure with high energy utilization rate and low power consumption, the structure being formed by N layers of SRAM circuits. The high voltage of the i SRAM circuit is shown in the description and the low voltage of the i SRAM circuit is shown in the description , wherein 1<=i<=N, N is greater than or equal to 1, and i and N are all positive integers. The power consumption of the SRAM array structure is low and the energy utilization ratio is high.

Application Domain

Digital storage

Technology Topic

High energyPower consumption +4

Image

  • A stacked SRAM array structure with high energy efficiency and low power consumption
  • A stacked SRAM array structure with high energy efficiency and low power consumption
  • A stacked SRAM array structure with high energy efficiency and low power consumption

Examples

  • Experimental program(1)

Example Embodiment

[0032] Example one
[0033] Suppose the battery voltage of the stacked SRAM is 1.8V, the write enable signal is a square wave signal with a frequency of 10kHz, and the global clock signal is a square wave signal with a frequency of 20kHz. The power supply voltage of the obtained 4-layer stacked SRAM is maintained from top to bottom. Stable at 1.8V, 1.35V, 0.9V and 0.45V. At the same time, when the voltage range is 450mV, the write/read power consumption of an SRAM cell during each access is only 2.45pJ/acc and 2.18pJ/acc, and the highest output power consumption is only 60μW. The consumption deviation is within 10%, and the efficiency in the worst case is as high as 94%, achieving the purpose of low power consumption and high energy conversion efficiency.

PUM

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Description & Claims & Application Information

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