A stacked SRAM array structure with high energy efficiency and low power consumption

[0032] Example one

[0033] Suppose the battery voltage of the stacked SRAM is 1.8V, the write enable signal is a square wave signal with a frequency of 10kHz, and the global clock signal is a square wave signal with a frequency of 20kHz. The power supply voltage of the obtained 4-layer stacked SRAM is maintained from top to bottom. Stable at 1.8V, 1.35V, 0.9V and 0.45V. At the same time, when the voltage range is 450mV, the write/read power consumption of an SRAM cell during each access is only 2.45pJ/acc and 2.18pJ/acc, and the highest output power consumption is only 60μW. The consumption deviation is within 10%, and the efficiency in the worst case is as high as 94%, achieving the purpose of low power consumption and high energy conversion efficiency.