A stacked SRAM array structure with high energy efficiency and low power consumption

Abstract

The invention discloses a stacked SRAM array structure with high energy utilization rate and low power consumption, the structure being formed by N layers of SRAM circuits. The high voltage of the i SRAM circuit is shown in the description and the low voltage of the i SRAM circuit is shown in the description , wherein 1<=i<=N, N is greater than or equal to 1, and i and N are all positive integers. The power consumption of the SRAM array structure is low and the energy utilization ratio is high.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits and relates to a stacked SRAM array structure with high energy utilization rate and low power consumption. Background technique [0002] SRAM is currently widely used in various fields. We represent a bit of binary information by the different stable states it is in. When there is no external signal, the flip-flop can maintain a certain stable state for a long time, so it is also called a static memory. Due to the vigorous development of implantable and wearable devices, smart mobile terminals represented by operating systems such as Android have higher and higher requirements for processors. At the same time, the capacity of batteries is growing very slowly. , the demand for high energy utilization and low power consumption becomes more and more frequent. Static random access memory (SRAM) is one of the important components, and SRAM with low power consumption and high energy effic...

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Problems solved by technology

In the method of reducing the power supply voltage, a linear regulator or a step-down DC converter can be used, but the voltage conversion ratio (that is, the ratio of the output voltage to the input voltage) of this structure is very low, and due to the high conduction of the converter Loss and low output power, its energy utilization efficiency also becomes low

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