A design method and system for a high-order high-speed parametric reconfigurable fir filter resistant to radiation

Abstract

The invention discloses a design method and system for an anti-radiation high-speed high-speed parameter-reconfigurable FIR filter, wherein the method includes the following steps: (1) according to task requirements, determine the order N of the FIR filter; (2) ) According to the FPGA model, determine the number L of multiplier-adders included in a column of multiplier-adders; (3) if N≤L, adopt the low-order FIR filter design method based on the multiplier-adder hard core to complete the filter design; (4) If N>L, adopt the high-order FIR filter design method based on the multiplier-adder hard core to complete the filter design. The invention has the advantages of fast running speed, less occupied resources and high order, and is suitable for the design of the satellite payload FIR filter.

Description

technical field [0001] The invention belongs to the technical field of satellite navigation, and in particular relates to a design method and system of an anti-irradiation high-order high-speed parameter-reconfigurable FIR filter. Background technique [0002] FIR filters are widely used in the design of various navigation and communication satellite payloads due to their simple architecture and linear phase characteristics. At present, the realization of the FIR filter in the FPGA is mostly realized by the combination of the multiplier hard core and the SLICE in the FPGA. This method uses the multiplier hard core to realize the multiplication function, and the SLICE realizes the addition function. The implementation of this method is intuitive and simple, but it has the disadvantages of low running speed, large resource consumption, low order, easy to be affected by spatial irradiation, and FIR filter parameters cannot be reconstructed. In detail, the FIR filters used on s...

AI Technical Summary

Problems solved by technology

[0003] (1) Susceptible to Single Event Upset (SEU)

[0004] SRAM type FPGAs are susceptible to SEU and have low reliability

[0005] (2) Large resource consumption

[0006] A large number of multi-bit adders are used in the FIR filter, which consumes a lot of resources

[0007] (3) Timing is very tight

If the multi-bit adder is built with multi-stage SLICE, it will inevitably lead to a huge operation delay

The combinational logic delay between the two flip-flops is too large, which will cause the sequential logic to fail to meet the clock rate operation requirements

[0009] (4) low order

[0010] Due to the difficulty of taking into account the high operation rate and high order number when using SLICE, the use conditions and environment on the star are limited

[0011] (5) FIR filter parameters cannot be reconstructed

[0012] The FIR filter IP core provided by Xilinx cannot flexibly reconstruct the parameters of the FIR filter, resulting in a design that is not flexible enough to meet the needs of the design

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