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Packaging method of wafer chip and structure of wafer chip

A wafer-level chip and packaging method technology, which is applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc. The effect of small size and thin thickness

Active Publication Date: 2019-01-01
嘉盛半导体(苏州)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, under the requirements of this trend, it is difficult to meet the solderability requirements of the ball planting of current chip products simply and at low cost

Method used

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  • Packaging method of wafer chip and structure of wafer chip
  • Packaging method of wafer chip and structure of wafer chip
  • Packaging method of wafer chip and structure of wafer chip

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Embodiment Construction

[0023] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0024] It should be noted that when an element is referred to as being “disposed on” another element, it may be directly on the other element or there may also be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may a...

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Abstract

The present invention provides a packaging method of a wafer chip and a structure of a wafer chip. The method comprises the steps of: forming a conductive convex column on a welding pad at the front surface of a wafer; forming a welding column on the conductive convex column, wherein the section area of the welding column is not changed in the thickness direction; forming a first plastic layer atthe front surface of the wafer, the conductive convex column and the periphery of the welding column; and executing a thinning program for the first plastic layer to allow the welding column to be exposed. The packaging method of the wafer chip and the structure of the wafer chip are good in weldability, simple in preparation process, low in cost, high in yield, smaller in the packaging product size and thinner in thickness.

Description

technical field [0001] The invention relates to the technical field of chip packaging, in particular to a packaging method and structure of a wafer-level chip. Background technique [0002] The statements in this section only provide background information related to the present disclosure and may not constitute prior art. [0003] Wafer bump technology is to form metal bumps on the metal pads of the bare wafer through a series of processes to realize the electrical interconnection between the package and the outside world. In practice, balls can be planted on the metal studs, and the packaged chip product can be electrically connected to the outside by means of the ball planting. Among them, solderability is an index to test whether the ball planting can reliably achieve electrical connection with the outside world. [0004] Based on the development trend of thinner and lighter electronic equipment, the packaged chip products are required to be smaller in size and thinner...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L23/31H01L23/488
CPCH01L21/56H01L23/3107H01L24/13H01L2224/13013H01L2224/13111
Inventor 彭彧吴冬梅余训松陆峥
Owner 嘉盛半导体(苏州)有限公司
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