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A Charge Pump Circuit with Low Mismatch Rate for Delay Locked Loop

A delay phase-locked loop and charge pump technology, applied in the field of microelectronics, can solve the problems of large charge/discharge current mismatch rate, etc., and achieve the effects of reducing current glitches, reducing mismatch rate, and low mismatch rate

Active Publication Date: 2022-03-22
CHONGQING UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the charge pump circuit with this structure has effects such as charge injection and clock feedthrough, and the charge / discharge current mismatch rate of the charge pump circuit is relatively large.

Method used

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  • A Charge Pump Circuit with Low Mismatch Rate for Delay Locked Loop
  • A Charge Pump Circuit with Low Mismatch Rate for Delay Locked Loop
  • A Charge Pump Circuit with Low Mismatch Rate for Delay Locked Loop

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0030] A low-mismatch charge pump circuit for delay-locked loops, such as figure 2 As shown, it includes a bias circuit 1 with current compensation, a current wheel charge pump circuit 2 and a negative feedback current compensation circuit 3;

[0031] Wherein, the signal output terminal of the bias circuit 1 with current compensation is connected to the signal input terminal of the current wheel charge pump circuit 2, and the signal output terminal VCTRL of the current wheel charge pump circuit 2 is respectively connected to the current The signal input terminal of the compensated bias circuit 1 and the negative feedback current compensation circuit 3 , the signal output terminal of the negative feedback current compensation circuit 3 is connected to the signal input terminal of the current wheel charge pump circuit 2 .

[0032] The bias circuit 1 with current compensation provides a bias current with compensation characteristics for the current wheel charge pump circuit 2, a...

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PUM

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Abstract

The present invention claims a low mismatch rate charge pump circuit for delay phase-locked loops, which mainly includes a bias circuit with current compensation, a current wheel charge pump circuit and a negative feedback current compensation circuit. The use of virtual switch tubes in the current wheel charge pump circuit can effectively suppress the effects of charge injection and clock feedthrough, and add MOS capacitors composed of PMOS tube M18 to the source and drain terminals of PMOS tube M7 and the source and drain terminals of NMOS tube M16 respectively. And the MOS capacitor formed by the NMOS tube M6 can reduce the current glitch when the switch tubes of the charge pump circuit are opened or closed at the same time; the compensation current I 2 , compensation current I 4 , compensation current I 21 and the compensation current I 26 Introduced into a current wheel charge pump circuit, the mismatch rate of charge / discharge current of the charge pump circuit is reduced, thereby realizing a charge pump circuit with a low mismatch rate for a delay-locked loop.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a charge pump circuit with low mismatch rate for a delay phase-locked loop. Background technique [0002] The charge pump circuit is one of the main circuit modules of the delay-locked loop, and its performance characteristics directly affect the overall performance characteristics of the delay-locked loop; the main function of the charge pump circuit is to convert the digital pulse signal of the frequency detector into an analog signal. Controls the delay time of the voltage-controlled delay line in the delay-locked loop. [0003] figure 1 It is a traditional charge pump circuit, in which the current source I1 provides bias current for the charge pump circuit through the current mirror composed of NMOS transistor M1 and NMOS transistor M8, and the current source I2 passes through the current mirror composed of PMOS transistor M2 and PMOS transistor M3. The...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/089
CPCH03L7/0891
Inventor 周前能彭志强李红娟关晶晶王永泽
Owner CHONGQING UNIV OF POSTS & TELECOMM
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