A method of making a memory

Abstract

The invention provides a manufacturing method of a memory. After the floating gate is formed, the isolation structure between the floating gates is etched twice by using a patterned negative photoresist layer as a mask, and then the isolation structure and the floating gate An inter-gate dielectric layer and a control gate are sequentially formed on it. The present invention uses the negative photoresist layer as a mask to etch the isolation structure between the floating gates, which reduces or avoids the peeling or wrinkling of the photoresist in the first etching process, thereby reducing the The impact of peeling or wrinkling on the second etching enables the isolation structure to be etched to a predetermined depth, increases the wrapping area of ​​the inter-gate dielectric layer and the control gate to the floating gate, improves the coupling rate, and improves the performance of the device. Further, in the present invention, before the second etching of the isolation structure, the patterned negative photoresist layer is subjected to aerobic pretreatment, so that the interface of the photoresist layer can be repaired after the first etching , to further reduce the defects caused by the photoresist during the etching process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a memory. Background technique [0002] With the development of semiconductor process technology, a flash memory (Flash Memory) with a faster access speed has been developed in terms of storage devices. Flash memory has the ability to store, read and erase information multiple times, and has the characteristic that the stored information will not disappear after power off. Therefore, flash memory has become a non-volatile memory widely used in personal computers and electronic devices. [0003] The operating voltage, reading and erasing speed of the flash memory are related to the coupling ratio between the floating gate and the control gate. The coupling ratio refers to the parameter by which the voltage applied on the control gate couples to the floating gate. For the flash memory, the greater the coupling ratio, the lower the operating v...

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Problems solved by technology

[0005] However, if a wet etching process is used for the isolation structure, due to the isotropy of the wet etching, while ensuring the etching depth of the trench, it is easy to cause over-etching, which will affect the subsequently deposited inter-gate dielectric layer ( The coupling rate between ONO) and the floating gate has an adverse effect. If dry etching is used, although there will be no over-etching phenomenon, the floating gate will be damaged or trapped under the action of plasma (plasma), which will affect the floating gate. grid performance

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