A method of manufacturing a semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate includes a first region,the semiconductor substrate in the first region is provided with a first pseudo gate structure, and the first pseudo gate structure includes a first pseudo gate dielectric layer and a first pseudo gate formed on the first pseudo gate dielectric layer; removing the first pseudo gate so as to form a first groove exposing the first pseudo gate dielectric layer; forming a covering layer covering the bottom and side walls of the first groove; and carrying out etching to remove the first pseudo gate dielectric layer. According to the manufacturing method provided by the invention of the semiconductor device, the etching depth will not extend to two sides of the pseudo gate structure in the process of removing the pseudo gate dielectric layer, thereby avoiding a subsequently formed metal gate from being communicated with source and drain regions, and improving the yield and performance of the product.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor device. Background technique [0002] With the continuous improvement of the integration level of semiconductor devices and the reduction of technology nodes, the traditional gate dielectric layer continues to become thinner, and the leakage of transistors increases accordingly, causing problems such as waste of power consumption of semiconductor devices. In order to solve the above problems, the prior art provides a solution of replacing the polysilicon gate with a metal gate. Among them, the "gate last" process is a main process for forming high-K metal gate transistors. When the feature size of the device is further reduced, the gate-last process is often applied to the Fin Field Effect Transistor (FinFET) to meet the demand for device performance. [0003] The "gate-last" process also includes two methods: "high K first (HK-...

AI Technical Summary

Problems solved by technology

The depth of over-etching easily exceeds the protection of the spacer and extends to both sides, so as to communicate with the source and drain regions, so that a bridge will be formed between the subsequently formed metal gate and the source and drain regions, affecting the performance and yield of the chip

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