Semiconductor chip packaging structure and packaging method thereof

Abstract

The invention relates to the technical field of electronic chip assembly and discloses a semiconductor chip packaging structure, comprising a packaging shell. A semiconductor chip is fixedly mounted at the bottom of an inner cavity of the packaging shell; the semiconductor chip is covered with protective resin film; connectors are fixedly mounted on the four sides of the packaging shell; wires areelectrically connected to the four sides of the semiconductor chip; the other ends of the wires are electrically connected with the sides of the connectors. The semiconductor chip packaging structureand the packaging method thereof have the advantages that the semiconductor chip is treated with silicone grease superposition, the problem can be avoided that the overall area of the packaging shellis too large since a chip pacakaged in in-line packaged form is all laid in the packaging shell, the wire re-arranging layer distribution mode helps greatly save space that chip wires consume, the assembly mode herein can apply to the general trend of chip miniaturization, and the practicality of the semiconductor chip packaging structure is greatly improved.

Description

technical field [0001] The invention relates to the technical field of electronic chip assembly, in particular to a semiconductor chip packaging structure and a packaging method thereof. Background technique [0002] The semiconductor integrated circuit industry has experienced rapid growth, and technological advances in semiconductor integrated circuit materials and design have produced multiple generations of semiconductor integrated circuits, each generation of semiconductor integrated circuits has smaller and more complex circuits than the previous generation of semiconductor integrated circuits, However, these advances have also increased the complexity of processing and manufacturing semiconductor integrated circuits. [0003] Most of the existing chip assembly methods use dual-in-line packaging, which is one of the plug-in packages. The pins are drawn from both sides of the package. There are two types of packaging materials: plastic and ceramics. The structure of the...

AI Technical Summary

Problems solved by technology

[0004] Aiming at the deficiencies of the prior art, the present invention provides a semiconductor chip packaging structure and its packaging method, which has the advantages of being suitable for the development of chip miniaturization and facilitating chip heat dissipation, and solves the problem that most of the existing chip assembly methods use dual in-line insertion. Dual-in-line package is one of the plug-in packages. This package was suitable for PCB through-hole installation at that time, and the wiring and operation were more convenient. It is relatively large, which also hinders the miniaturization development of semiconductor packaging device assembly. The internal structure of the chip is cumbersome and complicated due to the means of DIP packaging. Due to the heat generated by semiconductors and various electronic components during operation, the internal temperature of the chip increases with the use time. And it is getting higher and higher, which has caused a great safety hazard.

Images