A dynamically reconfigurable convolution neural network accelerator architecture oriented to the field of the Internet of things

Abstract

The invention relates to a dynamic reconfigurable convolution neural network accelerator architecture oriented to the field of the Internet of things, comprising a buffer architecture and the like. The buffer architecture is used for storing data from a storage external memory or data generated in the calculation process, organizing the buffer architecture, arranging the buffer architecture, and transmitting the buffer architecture to a processing unit array for calculation. A processing unit array is used for receiving the data from the cache architecture and storing the data in the cache architecture after the convolution operation processing. A computing module is used for receiving data from the array of processing units, selecting three operations of pooling, standardizing, or activating functions, and storing the output data in the buffer architecture. A controller is used to send commands to the cache architecture, the array of processing units and the computing module, and is designed with an external interface for communicating with the external system. The invention improves the performance of the convolution neural network accelerator and reduces the power consumption bydesigning a processing unit array with high parallelism and high utilization ratio and a buffer structure capable of improving the data multiplexing rate.

Description

technical field [0001] The invention belongs to the field of neural network accelerators, and in particular relates to a dynamically reconfigurable convolutional neural network accelerator architecture oriented to the field of Internet of Things. Background technique [0002] Artificial intelligence is one of the most popular computer sciences at present. As the main way to realize artificial intelligence, deep learning has also achieved far-reaching development. With the increase of the number of network layers and the number of neurons in each layer, the computational complexity of the model will increase. As the size of the network increases, it grows exponentially. Therefore, the learning speed and running speed bottleneck of deep learning algorithms are increasingly dependent on large-scale computing platforms such as cloud computing. For the hardware acceleration of deep learning algorithms, there are usually three types of implementations - multi-core CPU, GPU and FP...

AI Technical Summary

Problems solved by technology

However, the existing hardware implementation has high power consumption and low energy efficiency (performance / power consumption), and cannot be applied to smart mobile terminals, such as smartphones, wearable devices or self-driving cars. Wait

In this context, reconfigurable processors have been proven to be a form of parallel computing architecture with both high flexibility and high energy efficiency. Improving processing performance while using a dedicated processor is one of the solutions to the limitations of the further development of multi-core CPU and FPGA technology, and may become one of the solutions for realizing high-performance deep learning SoC in the future

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