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Semiconductor device and formation method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their formation, can solve problems such as size reduction, electrical performance and yield need to be improved, and achieve the effect of flexible formation

Active Publication Date: 2019-04-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, as the density of semiconductor devices increases and the size shrinks, the electrical performance and yield of semiconductor devices composed of fin field effect transistors still need to be improved.

Method used

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  • Semiconductor device and formation method thereof
  • Semiconductor device and formation method thereof
  • Semiconductor device and formation method thereof

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Experimental program
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Embodiment Construction

[0031] As mentioned in the background art, as the density of semiconductor devices increases and the size shrinks, the performance and reliability of the formed fin field effect transistors deteriorate. It will be described below in conjunction with the accompanying drawings.

[0032] Figure 1 to Figure 5 It is a schematic cross-sectional structure diagram of the formation process of a semiconductor device.

[0033] Please refer to figure 1 , a substrate 100 is provided, the substrate has a first region A and a second region B, and the second region B is located around the first region A.

[0034] Fins 101 are provided on the substrate, fins 101 are provided on the first region A and the second region B, and a pad mask layer 102 is provided on the top of the fins 101, and a pad mask layer 102 is provided on the fins and the substrate. An oxide layer 103 is formed on the substrate, the oxide layer 103 covers the substrate, the sidewall of the fin and the sidewall of the pad...

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PUM

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Abstract

The invention relates to a semiconductor device and a formation method thereof. The method comprises the steps of providing a substrate, wherein a first fin part and a second fin part are arranged onthe substrate, and the second fin part is arranged around the first fin part; forming a first isolation layer on the substrate, wherein the first isolation layer covers side walls of the first fin part and the second fin part, and the tops of the first fin part and the second fin part are exposed; removing the second fin part, and forming a second opening in the first isolation layer; forming a second isolation layer in the second opening; and etching the first isolation layer and the second isolation layer in the second opening until the top and a part of a side wall of a main fin part are exposed to form an isolation structure. The fin parts are effectively protected by the first isolation layer, the pollution of the effective fin parts during the formation process of the second isolation layer to cause damage to the fin parts is prevented, and the device performance is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. The gate size of planar transistors is getting smaller and smaller, so the gate's ability to control the channel current becomes weaker. It is easy to produce short channel effect, causing leakage current problems, and then affecting the electrical performance of semiconductor devices. [0003] In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fin field effect transistor (Fin FET), a common multi-gate device when the fin field effect transistor is used. The structure of the fin field effect transistor includes : the fin and the dielectric layer ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/06
CPCH01L29/0642H01L29/66795
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP