Semiconductor structure and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as easy cracks
Active Publication Date: 2019-06-18
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology
[0005] The main purpose of this application is to provide a semiconductor structure and its manufacturing method to solve the problem in the prior art that cracks are easily generated when materials with higher stress are formed into thicker structural layers
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Embodiment
[0048] The semiconductor structure includes a substrate and a waveguide arranged on the surface of the substrate, and the specific manufacturing process includes:
[0049] providing a substrate 10;
[0050] A thermal silicon dioxide layer of 2-4 μm is grown on the substrate 10 by heating and cooling several times to form figure 1 the lower cladding 20 shown;
[0051] On the surface of the lower cladding layer 20 away from the substrate 10, the first deposition step is carried out by LPCVD method, and 250 nm of Si is deposited. 3 N 4 , forming the first pre-structure sublayer 30, and then performing the first annealing step for annealing, the annealing temperature is between 1100°C, and the annealing time is 3h, forming figure 2 the structure shown;
[0052] On the surface of the first pre-structure sub-layer 30 away from the lower cladding layer 20, the second deposition step is carried out by LPCVD method, and 250 nm of Si is deposited. 3 N 4 , forming the second pre-...
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Abstract
The invention provides a semiconductor structure and a manufacturing method thereof. The method comprises a manufacturing process of a structural layer with a stress greater than or equal to 1 GPa. The manufacturing process of the structural layer comprises multiple deposition steps of depositing a pre-structure sub-layer on the surface of a substrate or on the surface of a deposited pre-structuresub-layer, wherein the thickness of the pre-structure sub-layer ranges from 100 nm to 400 nm; an etching step of annealing a pre-structure sub-layer with the thickness larger than 400 nm or etching multiple pre-structure sub-layers with the total thickness larger than 400 nm under the condition that the thickness of a pre-structure sub-layer or the total thickness of the multiple pre-structure sub-layers is larger than 400 nm after the deposition steps, wherein at least one etching step enables the projections of the etched pre-structure sub-layers on the surface of the substrate to coincide;and an annealing step after the etching step. The structural layer in the semiconductor structure obtained by the manufacturing method has relatively few cracks.
Description
technical field [0001] The present application relates to the technical field of semiconductors, in particular, to a semiconductor structure and a manufacturing method thereof. Background technique [0002] In the existing semiconductor field, when a structural layer with a large thickness and a large material stress is grown, the internal stress of the structural layer is large and cracks are likely to occur, resulting in poor quality of the structural layer, which in turn makes the performance of the device including the structural layer poor. [0003] For example, silicon nitride (Si 3 N 4 ), the material has developed extremely rapidly in the field of optoelectronics and has become a research hotspot at home and abroad. Si 3 N 4 With its following advantages, large bandgap (E=5.1ev), high refractive index (n=2.0), low optical transmission loss, compatible with CMOS process and low cost, it is widely used in silicon-based optoelectronic devices. Si in waveguide 3 N...
Claims
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Inventor 熊文娟张鹏刘若男李志华李俊峰赵超王文武亨利·H·阿达姆松
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI