Negative capacitance field effect transistor and preparation method thereof

Abstract

The invention provides a negative capacitance field effect transistor and a preparation method thereof. The negative capacitance field effect transistor comprises a substrate structure, a gate insulating dielectric layer and a metal gate stack; wherein the substrate structure comprises an MOS region, the gate insulating dielectric layer structure covers the MOS region and comprises an interface oxide layer and a ferroelectric graded layer sequentially stacked along the direction away from the substrate structure, wherein the ferroelectric graded layer is made of doped ferroelectric material, the doping concentration of the ferroelectric graded layer gradually changes along the direction away from the substrate structure, and the ferroelectric material gradually changes from HfO2 to HfxA1-xO2, wherein A is a doping element, and x is more than 0 and less than 1; and the metal gate stack covers the gate insulating dielectric layer structure. The ferroelectric graded layer can change the size and trend of the crystal lattice and the crystal grain of HfxA1-xO2 through the crystal lattice strain or the induction of metal elements, thereby improving the ferroelectric property, material stability and reliability of the NCFET by improving the electric domain polarity of the ferroelectric material

Description

technical field [0001] The invention relates to the technical field of semiconductor integration, in particular to a negative capacitance field effect transistor and a preparation method thereof. Background technique [0002] In the future, integrated circuits will continue to develop. In addition to the continuous improvement of integration density, the power consumption of circuits will become more and more important. Continuously reducing the operating voltage VDD and reducing device leakage become the key technology. Using new structures such as GAA can partially achieve the above goals, but when VDD needs to be continuously reduced to below 0.5V, the Boltzmann limit of transistor subthreshold swing (SS≥60mV / dec) becomes a key technical challenge. The development of new technologies that break through the limitations of SS has become a key direction for future new technologies. [0003] In addition to TFETs based on quantum tunneling, a ferroelectric capacitor based on...

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Problems solved by technology

[0007] However, with the continuous development of semiconductor devices, the polarity of the above-mentioned ferroelectric materials has gradually been unable to be satisfied. Therefore, it is urgent to provide a limited A method to continue to increase the polarity of ferroelectric materials in the gate space

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