TSV (Through-Silicon-Via) packaging structure and preparation method thereof

Abstract

The invention discloses a TSV (Through-Silicon-Via) packaging structure. The TSV packaging structure comprises a TSV wafer and a reinforcement structure, wherein the TSV wafer comprises a plurality offirst vias etched in a run-through mode; the inner walls of the first vias are coated with conducting materials so as to electrically conduct the front side and the reverse side of the TSV wafer; connection lines are selectively laid at the reverse side and on the lateral surface of the TSV wafer; the reinforcement structure is assembled to the reverse side of the TSV wafer; the reinforcement structure comprises first electrical connection ends facing away from the reserve side of the TSV wafer and second electrical connection ends abutted and electrically conducted with the connection lines;and the first electrical connection ends and the second electrical connection ends are electrically conducted. According to the TSV packaging structure disclosed by the invention, by assembling the reinforcement structure to the TSV wafer, when low CTE (Coefficient of Thermal Expansion), high intensity and a high modulus are ensured, high intensity and low warping of packaging are also ensured. Meanwhile, a preparation method of the TSV packaging structure, which is disclosed by the invention, can simultaneously meet requirements for reducing TSV cost and ensuring packaging intensity and warping.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and in particular relates to a TSV packaging structure and a preparation method thereof. Background technique [0002] TSV (Through-Silicon-Via) is formed by etching a vertical through-hole or a through-hole and through-hole through the substrate and filling the through-hole with a conductive material such as copper, or forming a conductive circuit on the sidewall of the through-hole . The TSVs may be used to provide electrical connection from the backside of the semiconductor substrate to semiconductor circuitry on the opposite side of the substrate, or to semiconductor circuitry of stacked die. [0003] In the existing technology, due to the technical and cost challenges of TSV, in order to realize narrow-pitch interconnection, TSV holes with high aspect ratio are limited by equipment and process, and it is necessary to thin the chip or interposer to a thickness below 150 microns ; ...

AI Technical Summary

Problems solved by technology

[0003] In the existing technology, due to the technical and cost challenges of TSV, in order to realize narrow-pitch interconnection, TSV holes with high aspect ratio are limited by equipment and process, and it is necessary to thin the chip or interposer to a thickness below 150 microns ; If so designed, it will bring huge challenges to subsequent processes such as holding and assembling

At the same time, in order to ensure the structural strength, it is necessary to carry out plastic sealing on the back and side, but due to the limitation of the strength of the plastic sealing compound, only the plastic sealing on the back and side cannot completely guarantee the overall structural strength

In addition, due to the CTE (coefficient of thermal expansion) mismatch between the mold compound and the chip, it will cause warpage problems

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