A wafer level chip scale package and a manufacturing method thereof

Abstract

A wafer level chip scale package and a manufacturing method thereof are disclosed. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) circuits connected to a silicon wafer through openings of a first polymer layer, with the openings penetrating the first polymer layer to connect the redistribution layer circuits to metal pads on a top surface of the silicon wafer; a plurality of underbump metal (UBM) layers each of which is in contact with one of the plurality of RDL circuits through openings in a second polymer layer over the first polymer layer; a plurality of solder bumps which lie on each UBM layer; a metal plating layer which lies under the first polymer layer and does not contact any of the plurality of RDL circuits; and at least one separator which lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL circuits or an air gap between the two neighboring RDL circuits.

Description

technical field [0001] The present invention relates to a wafer packaging technology, and in particular to reduce crosstalk interference, copper migration, and leakage current in wafer-level die size packaging. Background technique [0002] Based on the fact that semiconductor chips, wafers, or integrated circuits may encounter physical damage when connected to the applied printed circuit board, or during user operation, in order to achieve the purpose of protecting these circuits, these integrated Proper packaging of the circuit is necessary. For example, several common package types currently on the market include: lead frame packages, ball grid array packages, and chip scale packages, such as: wafer-level Grain size package (wafer level chip scale package) and so on. [0003] Among them, the wafer-level chip size package (WLCSP) has the smallest form factor, because its package size is at the same level as the wafer size, and it has good electrical, structural, and ther...

AI Technical Summary

Problems solved by technology

Under the condition of this thickness, there is a high probability that there will be a problem of chip winding when the assembly process is in progress

And this is why most component suppliers limit the density of the redistribution layer to only 75% of the unit assembly area. In other words, 25% of the area of ​​the chip does not have a redistribution layer or copper wire. This also causes the problem of an increase in the thermal resistance of the component or a decrease in thermal characteristics

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