Analog-to-Digital Converter Error Shaping Circuit and Successive Approximation Analog-to-Digital Converter

Abstract

The invention discloses an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter, wherein the analog-to-digital converter error shaping circuit includes a distributed capacitor array, a data weighted average module, a mismatch error shaping module, and a control logic generating circuit, digital filter and extractor, the distributed capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high rank and a second sub-capacitor array of a low rank, and the data weighted average The module eliminates the correlation between the first sub-capacitor array and the input signal, and the mismatch error shaping module eliminates the correlation between the second sub-capacitor array and the input signal, thereby reducing the error of the capacitor array and improving the capacitance without increasing the area of ​​the capacitor array. The linearity of the DAC capacitor array solves the limitation of the capacitor array for high-precision SAR ADC.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. Background technique [0002] For ultra-high-precision successive-approximation ADCs (including oversampling ADCs and noise-shaping ADCs), the linearity of the capacitor array is a major limiting factor because oversampling techniques are only effective for reducing quantization noise, The nonlinearity of the capacitor array will cause harmonics, these harmonic components are distributed in the signal band, and oversampling techniques cannot eliminate them. [0003] Among them, trace parasitics and unit capacitance mismatch are two factors that affect linearity. Ideally, the nonlinear error introduced by trace parasitics in the capacitor array can be solved through perfect circuit and layout design. Unit capacitance mismatch is also a factor. ...

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Problems solved by technology

[0002] For ultra-high-precision successive-approximation ADCs (including oversampling ADCs and noise-shaping ADCs), the linearity of the capacitor array is a major limiting factor because oversampling techniques are only effective for reducing quantization noise, The nonlinearity of the capacitor array will cause harmonics, these harmonic components are distributed in the signal band, and oversampling technology cannot eliminate them

[0003] Among them, trace parasitics and unit capacitance mismatch are two factors that affect linearity. Ideally, the nonlinear error introduced by trace parasitics in the capacitor array can be solved through perfect circuit and layout design. Unit capacitance mismatch is also a factor. It is a difficult problem to solve because it is only related to process precision parameters and capacitor size, and the mismatch is inversely proportional to the square root of the capacitor size. 4 times the capacitor size can only increase the linearity by 6dB at most. For example, a suitable circuit and layout designed capacitor arrays, such as figure 1 As shown, the MSB capacitor array with 7bits binary weight is added to the LSB capacitor array with 5bits binary weight, and a bridge capacitor is used in the middle to attenuate from LSB to MSB. 1C represents a unit capacitance, and its total size is about 1pF, which can provide 70dB The linearity of the DAC can meet the requirements of a 12bits SAR ADC for the DAC capacitor array. For a 14bits SAR ADC, the linearity of the capacitor array needs to be increased to 4 times that is 12dB. At this time, the total size of the capacitor array needs to be at least 16pF, although it greatly increases power consumption and layout area, it is still within an acceptable range

But if it is a 16bits SAR ADC, for a similar design, the total size of the capacitor needs to reach 256pF to meet the linearity requirement of the capacitor array, which is an unacceptable size for both power consumption and area

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