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Fused-multiply-add floating-point operations on 128 bit wide operands

A technology of operands and floating point units, which is applied in calculation, data conversion, electrical digital data processing, etc., can solve the problem of reducing the attractiveness of big data analysis, and achieve the effect of saving circuit area

Active Publication Date: 2019-08-23
IBM CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The described methods are typically one to two orders of magnitude slower than hardware implementations, making them less attractive for big data analysis

Method used

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  • Fused-multiply-add floating-point operations on 128 bit wide operands
  • Fused-multiply-add floating-point operations on 128 bit wide operands
  • Fused-multiply-add floating-point operations on 128 bit wide operands

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Embodiment Construction

[0047] In the figures, the same elements are denoted by the same reference numerals. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. Moreover, the drawings are intended to depict only typical embodiments of the invention and therefore should not be considered as limiting the scope of the invention.

[0048] The illustrative embodiments described herein provide units, methods, systems, and computer program products for implementing a fused multiply-add operation (FMA) on three 128-bit wide operands. For clarity of description, the illustrative embodiments are sometimes described herein using specific techniques as examples only.

[0049] The illustrative embodiments may be used to implement a fused multiply-accumulate operation on three 128-bit wide operands on the floating point unit of the present invention.

[0050] figure 1 Depicts the data flow of a floating point unit 10 for performing binary floating poi...

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Abstract

A floating-point unit (10) is configured to implement a fused-multiply-add operation on three 128 bit wide operands (100, 102, 104), and comprises: (i) a 113*113-bit multiplier (14); (ii) a left shifter (18); (iii) a right shifter (20); (iv) a select circuit (24) comprising a 3-to-2 compressor (25); (v) an adder (26) connected to the dataflow from the select circuit (24); (vi) a first feedback path (36) connecting a carry output (91) of the adder (26) to the select circuit (24); (vii) a second feedback path (38) connecting the output of the adder (26) to the shifters (18, 20) for passing an intermediate wide result (86) through the shifters (18, 20).

Description

technical field [0001] The present invention relates generally to data processing systems, and more particularly to units, methods, systems and computer program products for performing fused multiply-add floating point operations on 128-bit wide operands. Background technique [0002] The IEEE-754-2008 Standard for Binary Floating-Point Arithmetic, published in 2008, specifies a floating-point data architecture that is typically implemented in computer hardware, such as a floating-point processor with a multiplier. The format consists of signed, unsigned offset exponent, and significand. The sign bit is a single bit, denoted by "S". The unsigned offset exponent denoted by "e" is, for example, 8 bits long for single precision, 11 bits long for double precision, and 15 bits long for quad precision. The significand is, for example, 24 bits long for single precision, 53 bits long for double precision, and 113 bits long for quad precision. As defined by the IEEE-754-2008 stand...

Claims

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Application Information

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IPC IPC(8): G06F7/483
CPCG06F7/5443G06F7/483G06F5/012
Inventor M·K·克罗纳U·克劳兹T·巴宾斯基S·M·穆勒A·瓦格纳
Owner IBM CORP