Method of forming 3D NAND memory

Abstract

The invention provides a method of forming a 3D NAND memory, and the method comprises the steps: etching a stacking structure to form a plurality of grid separation grooves penetrating through the stacking structure, and then forming filling layers in the grid separation grooves, wherein the grid separation grooves are filled with the filling layers; after the filling layer is formed, etching the stacking structures at the two sides of the gate isolation grooves to form a plurality of channel through holes penetrating through the stacking structures; forming a storage structure in the channel through hole; after the storage structure is formed, removing the filling layer, and exposing the gate isolation groove; removing a sacrificial layer, and correspondingly forming a control gate at a position where the sacrificial layer is removed; and forming an array common source in the gate isolation groove. In the invention, because the step of forming the gate isolation groove is executed before the step of forming the channel through hole and the step of forming the storage structure in the channel through hole, the gate isolation grooves do not incline, thereby preventing the gate isolation grooves and the channel through hole from being short-circuited.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for reducing 3D NAND memory. Background technique [0002] NAND flash memory is a non-volatile storage product with low power consumption, light weight and good performance, and has been widely used in electronic products. At present, the NAND flash memory with a planar structure is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory with a 3D structure is proposed. [0003] The formation process of the existing 3D NAND memory generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on the substrate; etching the stacked structure, forming channel vias in the stacked structure, and forming channel vias Finally, etch the substrate at the bottom of the channel via hole to form a groove in the substrate; in ...

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Problems solved by technology

[0004] Existing memories generally include several memory blocks (Blocks), and the memory blocks are generally separated by Gate Line Slits (GLS) vertically penetrating the stacked structure. However, existing 3D NAND memories During the process, the gate spacer in some areas is easy to tilt, resulting in a short circuit between the gate spacer and the channel via hole

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