Design method of two-dimensional Fourier transform IP core based on HLS

A technology of Fourier transform and two-dimensional Fourier transform, which is applied in the field of image processing, can solve the problems of algorithm real-time influence and time-consuming, and achieve the effect of improving industrial practicability

Inactive Publication Date: 2019-10-11
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

[0004] Two-dimensional Fourier transform is a commonly used technology in image processing, and it is usually a relatively complicated process in the image processing process. It takes a lot of time to process a large amount of image data. Even if two-dimensional fast Fourier transform is used, it will still affect the implementation of the algorithm. real-time impact

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  • Design method of two-dimensional Fourier transform IP core based on HLS
  • Design method of two-dimensional Fourier transform IP core based on HLS
  • Design method of two-dimensional Fourier transform IP core based on HLS

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[0041] Embodiments of the invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

[0042] according to figure 1 , a design method of a two-dimensional Fourier transform IP core based on HLS, comprising the following steps:

[0043] 1) The two-dimensional Fourier transform in image processing is split into two one-dimensional Fourier transforms, and the IP core is designed according to the size of the image to be processed. Assuming that the image size is 256*128, two one-dimensional The dimensions processed by the four-dimensional Fourier transform are 256 and 128 respectively;

[0044] 2) The one-dimensional Fourier transform adopts the base-2 fast Fourier transform, which reduces the required calculation steps and accelerates the calculation speed ...

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Abstract

The invention discloses a design method of a two-dimensional Fourier transform IP core based on HLS. The design method specifically comprises the following steps: splitting two-dimensional Fourier transform in image processing into two one-dimensional Fourier transforms; calculating the one-dimensional Fourier transform by using a DIT radix-2 fast Fourier calculation method; adopting an HLS tool to design a one-dimensional Fourier transform IP core with the processing lengths of 256 and 128, including acceleration design of a twiddle factor, design of a reverse order and design of inverse Fourier transform. According to the invention, the two-dimensional Fourier transform is split; one-dimensional Fourier transform is respectively designed by adopting fast Fourier transform; acceleration is realized in the aspect of software by using a simplified algorithm, hardware IP core design is performed by using HLS, acceleration is realized in the aspect of hardware by using parallel computing,and after two-dimensional Fourier transform in an image processing technology is accelerated, real-time design of algorithm processing is facilitated, and the industrial practicability of an image processing algorithm is improved.

Description

technical field [0001] The invention relates to a design method of a two-dimensional Fourier transform IP core, in particular to a design method of an HLS-based two-dimensional Fourier transform IP core, and belongs to the technical field of image processing. Background technique [0002] With the maturity of image processing theory, computer vision technology has been widely used in various fields. The biggest problem affecting the practical engineering application of computer vision is the poor real-time calculation. Since a large amount of data needs to be processed in the image processing process, the high parallel capability of the FPGA can be used for calculation, and the algorithm can be accelerated by designing the hardware IP (Intellectual Property, intellectual property) core of the image processing algorithm. [0003] The design of the hardware acceleration IP core can be directly written by the hardware description language Verilog HDL, used for relatively simpl...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50G06F17/14
CPCG06F17/142G06F30/20
Inventor 曹云峰王鹏许蕾丁萌庄丽葵王朝阳马宁
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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