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A Fault-Tolerant Routing Method for Area Fault Awareness in Wireless Network-on-Chip

A network-on-a-chip, trouble-free technology, applied in wireless communication, data exchange network, network traffic/resource management, etc., can solve the problem of unbalanced network load and not taking into account the generation of hot spots.

Active Publication Date: 2021-05-04
HEFEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

These methods do not take into account that hot spots will be generated around the fault, resulting in the problem of unbalanced network load.

Method used

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  • A Fault-Tolerant Routing Method for Area Fault Awareness in Wireless Network-on-Chip
  • A Fault-Tolerant Routing Method for Area Fault Awareness in Wireless Network-on-Chip
  • A Fault-Tolerant Routing Method for Area Fault Awareness in Wireless Network-on-Chip

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Embodiment Construction

[0050] In this embodiment, a fault-tolerant routing method for regional fault awareness in wireless on-chip networks is: adjacent wired nodes adopt information exchange based on fault areas, which can make nodes perceive the fault state around them, and fill the one-hop information exchange well. Insufficient; the information of the wireless node is exchanged in a two-hop sensing way, which avoids the congestion of the surrounding routers when the wireless node fails or is congested; the proposed method does not use more wiring and area overhead, and through the clever combination of routing algorithms to improve performance.

[0051] In order to simplify the position selection of the destination node relative to the current node, firstly, the area of ​​the destination node relative to the current node is divided into four directions (New, Ens, Sew, Wns). In order to optimize the selection of output ports while also providing a high degree of adaptability to the routing algori...

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Abstract

The invention discloses a fault-tolerant routing method for regional fault perception in a wireless on-chip network. The steps include: 1. Judging whether a data packet is transmitted through a wired link or a wireless link, and judging based on the number of hops to a destination node; 2. Select the direction of the data packet routing, and select the direction with a lower degree of failure and congestion for data packet transmission. The invention can subtly integrate fault information and congestion information in the wireless on-chip network to select the best path for data packet routing, thereby well balancing the network load in the faulty network.

Description

technical field [0001] The invention belongs to the application technical field of integrated circuit chip design, and more specifically relates to a fault-tolerant routing algorithm for Regional Fault Awareness (RFA) with low delay in a wireless on-chip network. Background technique [0002] As silicon technology continues to advance, large chip multiprocessors (CMPs) and systems-on-chips (SoCs) are gradually becoming mainstream designs. Network-on-Chip (NoC) technology can integrate various processors and on-chip memory into one chip, and has become a cutting-edge communication architecture on the chip. Although NoCs have their advantages, as the number of processors increases and integrated circuits (ICs) become more complex, an important performance limitation of traditional NoCs comes from the multi-hop communication of planar metal interconnects, two of which are far apart. Data transmission between distant nodes results in high latency and power consumption. Accordi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L12/703H04L12/803H04W28/02H04W40/02H04L12/933H04L45/28
CPCH04L45/28H04L47/122H04W28/0289H04W40/02H04L49/109
Inventor 欧阳一鸣汝孟轩梁华国王奇李建华
Owner HEFEI UNIV OF TECH
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