A Hybrid SRAM Cell Circuit of 10t TFET and MOSFET Devices with High Write Margin

Abstract

The invention discloses a 10T TFET and MOSFET device hybrid SRAM unit circuit with high write margin. The combination of MOSFET devices not only overcomes the shortcoming of weak transmission capability of stacked TFETs, but also avoids the problem of P-I-N forward bias current when TFET devices are used as SRAM unit transmission tubes. The write ability of the unit is improved, and the static power consumption of the unit is reduced.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a 10T TFET and MOSFET device hybrid SRAM unit circuit with high writing margin. Background technique [0002] With the development of mobile electronic products, people's demand for low power consumption of integrated circuits has become more and more urgent. In recent years, MOSFET (Metal-Oxide Semiconductor Field Effect Crystal) has become an important part of digital integrated circuits and analog integrated circuits. However, with the development of integrated circuit technology nodes, the size of MOSFET is gradually reduced. Due to the short channel effect of MOSFET, its ability to turn off at sub-threshold voltage is weakened, which increases the static leakage current and static power consumption of the circuit. In a microprocessor, static random access memory (SRAM) occupies more than 50% of the chip area and consumes most of the static power consumption of the p...

AI Technical Summary

Problems solved by technology

Although this structure perfectly solves the problem of the P-I-N forward bias current of TFETs, stacking TFETs leads to very weak writing ability of the cells, and the cells cannot even be written successfully in the smallest size (as shown in Table 1)

In order to realize the write function, the size of the transmission tube must be increased, resulting in an increase in unit area and an increase in chip cost

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