1.5T SONOS flash memory device and process method thereof

Abstract

The present invention discloses a 1.5T SONOS flash memory device. The 1.5T SONOS flash memory device comprises a memory cell area and a logic area divided on a semiconductor substrate; the memory cellarea is arranged in a P well in the semiconductor substrate, and the logic area is arranged in a tube well area of the CMOS (Complementary Metal-Oxide-Semiconductor Transistor); selection tubes and astorage tube are formed in the memory cell area, the selection tubes are arranged at the center of the memory cell area, and the two selection tubes share a source area; and the polysilicon gate of the logic area and the polysilicon gate of the selection tube are formed by etching the same layer of polysilicon at one time. According to the 1.5T SONOS flash memory device provided by the present invention, the polysilicon gate of the devices in the logic area and the polysilicon gate of the selection tubes in the memory cell area are formed by etching the same layer of polysilicon, and adjustment and injection of the well and the threshold voltage of the devices in the logic area are performed before the first layer of polysilicon is deposited, so that he thickness of the polysilicon gate of the storage tube is not limited by the process technology of the devices in the logic area, and process integration can be facilitated.

Description

technical field [0001] The invention relates to the field of manufacturing technology of semiconductor devices, in particular to a 1.5T SONOS flash memory device and a process method of the 1.5T SONOS flash memory device. Background technique [0002] The cell structure of silicon-oxide-nitride-oxide-silicon (Silicon-Oxide-Nitride-Oxide-Silicon, S0N0S) memory comprises a storage unit (cell) tube and a selector tube, and the gate dielectric layer of two devices is in The vertical electric field strength that the memory bears during operation is greater than that of the CMOS device, so both devices have a large GIDL leakage current. The channel of the cell tube of the SONOS memory has been doped with higher concentration of N-type impurities to form a depletion zone, and the doping concentration of the lightly doped drain (LDD) required by the cell tube is lower than that of the selector tube. However, the selection tube and the cell tube share LDD and HALO ion implantation, ...

AI Technical Summary

Problems solved by technology

However, the inherent disadvantage of the 2T structure is its large chip area loss.

In the 2T structure, there are common doped regions and source and drain regions between the two polysilicon gates, which makes the distance between the polysilicon gates larger, thus occupying a larger area

[0008] Since the existing 1.5T SONOS memory manufacturing process is to synchronously manufacture the polysilicon gate of the storage tube and the polysilicon gate of the logic area, the thickness of the polysilicon gate of the storage tube will be limited by the thickness of the polysilicon gate of the logic area , is not conducive to process integration

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