Semiconductor device structure and forming method thereof

Abstract

The disclosure relates to a semiconductor device structure and a forming method thereof. The method comprises the steps: generating a first dielectric layer on a substrate, performing P type impurityion implantation and N type impurity ion implantation on the first dielectric layer to form a P-layer and a JFET layer; taking the middle region of the JEFT layer as a JFET region of a semiconductor device structure, and performing ion implantation on two sides of the JEFT region to form a body region of the semiconductor device structure; and performing ion implantation on the part of the body region to form a source region of the semiconductor device structure. According to the embodiment of the invention, the JFET region is arranged at the semiconductor device structures, so that the characteristic conduction resistance of the semiconductor device is reduced and thus the conduction speed is increased and the switching power loss is reduced. Moreover, because the P-region is arranged atthe JFET region, the gate oxidation reliability of the device can be improved, the gate-drain capacitance of the device can be effectively reduced, and the switching power loss can be further reduced.

Description

technical field [0001] The present disclosure relates to the technical field of semiconductor technology, in particular to a semiconductor device structure and a method for forming the same. Background technique [0002] The traditional planar silicon carbide metal oxide semiconductor field effect transistor (Planar SiC MOSFET, such as vertical double diffused metal oxide transistor VDMOS) has a large device size, which affects the characteristic on-resistance of the device, which will increase the switching loss, resulting in The performance of the device is poor, and the cost of traditional planar silicon carbide devices is high, which is not conducive to popularization and utilization. Contents of the invention [0003] In view of this, the present disclosure proposes a method for generating a semiconductor device structure, the method comprising: [0004] Generate a first dielectric layer on the substrate, and perform P-type impurity ion implantation and N-type impuri...

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Problems solved by technology

[0002] The traditional planar silicon carbide metal oxide semiconductor field effect transistor (Planar SiC MOSFET, such as vertical double diffused metal oxide transistor VDMOS) has a large device size, which affects the characteristic on-resistance of the device, which will increase the switching loss, resulting in The performance of the device is poor, and the cost of traditional planar silicon carbide devices is high, which is not conducive to popularization and utilization

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