Low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and manufacturing method

Abstract

The invention relates to a low-gate charge low-on resistance deep trench power metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method. Shield grid conducting polycrystalline silicon bodies are arranged in cellular trenches of the device. The two sides of the shield grid conducting polycrystalline silicon body are provided with gate conducting polycrystalline silicon. An insulating gate oxide layer is arranged between the gate conducting polycrystalline silicon and the upper sidewall of the cellular trench. Second shield grid conducting polycrystalline silicon is arranged below the gate conducting polycrystalline silicon. A shield grid oxide layer covers the lower part of the shield grid conducting polycrystalline silicon. A trench opening of the cellular trench is covered by an insulating dielectric layer. The two sides of the cellular trench are provided with a contact hole respectively. Metal connecting wires are deposited on the insulating dielectric layer, are in ohmic contact with a first-conduction type source region and a second-conduction type well layer and realize gate conducting polycrystalline silicon electrical connection, shield grid conducting polycrystalline silicon body electrical connection and second shield grid conducting polycrystalline silicon electrical connection. The device is low in on resistance, gate-drain charge (Qgd), switching loss and cost and high in switching speed; and a process is simple.

Description

technical field [0001] The invention relates to a power MOSFET device and a manufacturing method thereof, in particular to a low gate charge and low on-resistance deep trench power MOSFET device and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background technique [0002] Trench power MOS devices have the characteristics of high integration, low on-resistance, fast switching speed, and low switching loss, and are widely used in various power management and switching conversions. With the development of industry and global warming, the climate environment is getting worse and worse. Countries have begun to pay more and more attention to energy saving, carbon reduction and sustainable development. Therefore, the requirements for power consumption and conversion efficiency of power MOS devices are getting higher and higher. The conduction loss is mainly composed of conduction loss and switching loss. The conduction loss is mainly a...

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Problems solved by technology

However, when the unit cell density increases, the corresponding gate charge will also increase, and it is difficult to reduce both the on-resistance and the gate charge at the same time; the second is to increase the doping concentration of the epitaxial wafer and reduce the thickness of the epitaxial layer, but this The method will reduce the source-drain breakdown voltage, so relying solely on reducing the doping concentration / reducing the thickness of the epitaxial layer is limited by the size requirement of the breakdown voltage

There are many ways to reduce the gate charge. For example, Hua Hong NEC Electronics’ patent application in China (publication number CN1877856A) proposed thick bottom oxide technology (Thick bottom oxide) to reduce the gate-to-drain capacitance Cgd, thereby reducing the gate charge. For the purpose of Qg, this technology reduces Qg by about 30%, but it still cannot meet the increasingly high frequency applications, and cannot significantly reduce the characteristic on-resistance at the same time

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