Groove type high-power MOS device and manufacturing method thereof

Abstract

The invention relates to an MOS device and a manufacturing method thereof, in particular to a groove type high-power MOS device and the manufacturing method thereof. According to the technical scheme provided by the invention, on the overlook plane of the MOS device, the groove type high-power MOS device comprises a cellular area on a semi-conductive substrate and a terminal protection structure,the cellular area is arranged in the central area of the semi-conductive substrate; the periphery of the cellular area is provided with the terminal protection structure which comprises a partial pressure protection area at the inner circle and a cutoff protection area at the outer circle; by deepening the depth and the concentration of a second conductive type layer in the partial pressure protection area, the peripheral curvature in the well region of the partial pressure protection area is increased, thus inhibiting electric field concentration and increasing the withstand voltage. The groove type high-power MOS device and the manufacturing method have the advantages of low resistance, high voltage-resistant capacity, high reliability, simple process and low cost.

Description

technical field [0001] The invention relates to a MOS device and a manufacturing method thereof, in particular to a trench type high-power MOS device and a manufacturing method thereof. Background technique [0002] The specific on-resistance (Specific Rdson) and breakdown characteristics of high-power MOS devices are two important aspects that determine product performance. On the premise of not affecting device performance, cost reduction is one of the core contents of design and manufacturing. At present, Chinese patent CN101459084A discloses a "planar double-diffused metal oxide semiconductor device and its manufacturing method", which uses planar double-diffusion technology to manufacture power MOS devices, and reduces the on-resistance of the device through JFET injection. [0003] Such as figure 1 Shown: is the structure of the power MOS device disclosed in Chinese patent CN101459084A, the conduction channel is formed by the lightly doped second conductivity type wel...

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Problems solved by technology

[0004] 1. It greatly restricts the integration of cells in a unit area, thus limiting the reduction space of the characteristic on-resistance of the device

[0005] 2. Between the two channels below the gate oxide, there is a junction field effect transistor on-resistance (JFET resistance) due to parasitic, and in the planar power MOS device, this part of the resistance occupies the entire device on-resistance More than 15%, so it becomes another important reason for limiting the on-resistance of device characteristics

[0008] 1. The depth of the second conductivity type well area in the cell area and the terminal protection area is the same, which limits the effect of withstand voltage and the reliability of withstand voltage

[0009] 2. The manufacturing process of the second conductivity type well region in the cell region and the terminal protection region is the same, which limits the adjustment of the process window for the second conductivity type well region in the cell region or the second conductivity type well region in the voltage division protection region. , thus limiting the withstand voltage effect of the MOS device

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