Semiconductor memory device and process method

Abstract

The invention provides a semiconductor memory device. Each bit line of the semiconductor memory device is of a multilayer structure and comprises a lower-layer conductive material, a middle-layer conductive material, an upper-layer conductive material and a top-layer hard mask layer. The lower-layer conductive material, the middle-layer conductive material and the upper-layer conductive material are sequentially stacked to form a multi-layer conductive structure. Bit line contact grooves are further formed in a semiconductor substrate, and the bit lines are located on an insulating interlayeron the surface of the semiconductor substrate and in the bit line contact grooves. The transverse contact area between the bit lines on the insulating interlayer and the insulating interlayer is large, and the transverse contact area between the bit lines in the bit line contact grooves and the bottoms of the bit line contact grooves is small, so that the transverse isolation effect between the bit lines is improved, and electric leakage is improved. According to the manufacturing process provided by the invention, the profile morphology with alternately changed transverse contact widths of different bit lines is completed in one step through the etching process, and additional process steps are not added.

Description

technical field [0001] The present invention relates to the field of semiconductor device design and manufacturing technology, in particular to a semiconductor storage device and a process method for the semiconductor storage device. Background technique [0002] Such as figure 1 Shown is a top view structural diagram of an existing semiconductor storage device, which includes a plurality of word lines WL extending in a first direction and parallel to each other. The word lines are formed by connecting the polysilicon control gates of the storage transistors. Between them is a contact plug or a device isolation layer, the second direction perpendicular to the word line is the bit line BL of the memory, and the area where the bit line BL and the word line WL intersect is the structure area of ​​the memory tube. The figure also has a strip-shaped active region ACT similar to a rod shape. In the traditional memory device structure, the active region ACT generally chooses the ...

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Problems solved by technology

[0011] The morphology of the bit line structure of conventional semiconductor storage devices in the semiconductor substrate is relatively symmetrical from top to bottom, and its cross-section has no obvious change in width. In the existing bit line structure, the interval SC between the bit lines is relatively small. Small

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