Structure and preparation method of silicon-based stress-compensating metal interlayer compound semiconductor wafer

Abstract

The invention discloses a structure and a preparation method of a compound semiconductor wafer with a silicon-based stress-compensating metal interlayer, which comprises from top to bottom: a compound semiconductor wafer, a metal layer M 1 , metal layer M 2 and silicon wafer; thermal expansion coefficient of compound semiconductor wafer > metal layer M 1 The thermal expansion coefficient of the silicon chip > the thermal expansion coefficient of the metal layer M 2 coefficient of thermal expansion; during preparation, grow a sacrificial layer on the compound semiconductor wafer; implant ions into the compound semiconductor wafer through the sacrificial layer; polish the sacrificial layer, remove or partially remove the sacrificial layer; A metal layer M is deposited on the remaining sacrificial layer 1 ; Clean and dry the silicon wafer; deposit a metal layer M on the silicon wafer 2 ; The metal layer M on the compound semiconductor wafer 1 and the metal layer M on the silicon wafer 2 Carry out bonding; after bonding, anneal the composite wafer, and peel off the excess compound semiconductor wafer at the position of implanted ions.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated devices, in particular to a structure and a preparation method of a silicon-based stress-compensating metal interlayer compound semiconductor wafer. Background technique [0002] With the continuous improvement of semiconductor technology level in recent decades, wafer bonding technology has attracted more and more attention. The size of devices based on silicon materials has gradually reached the physical limit, which has severely challenged Moore's law; therefore, III-V compound semiconductor materials are regarded as ideal alternative materials. [0003] A structure composed of a compound semiconductor wafer and silicon will be an ideal CMOS device, but there is a large difference in thermal expansion coefficient between the thermal expansion coefficient of the compound semiconductor wafer and that of silicon, which will cause a gap between the bonding interface. A large therm...

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Problems solved by technology

[0003] A structure composed of a compound semiconductor wafer and silicon will be an ideal CMOS device, but there is a large difference in thermal expansion coefficient between the thermal expansion coefficient of the compound semiconductor wafer and that of silicon, which will cause a gap between the bonding interface. The thermal stress will reduce the quality of the top-layer compound semiconductor wafer film, which will affect the optical and electrical performance of subsequent devices.