Static random access memory (SRAM) cell and related device

Abstract

The invention relates to a static random access memory (SRAM) unit and a related device, which are used for reducing the power consumption of an SRAM when an SRAM is accessed. The SRAM unit is locatedin an SRAM memory, the SRAM memory comprises an SRAM memory array composed of a plurality of SRAM units, and each SRAM unit comprises a memory circuit which is connected with a write-in circuit and aread-out circuit and used for storing data, the write-in circuit used for writing data into the storage circuit, and the read-out circuit for enabling data on a read bit line connected with the SRAMunit to be data stored in the storage circuit after the read enable signal is valid, wherein when the first number of the SRAM units storing the first data in the column where the SRAM units are located is larger than the second number of the SRAM units storing the second data, the read bit line is pre-charged to a high level; when the first number is less than the second number, the read bit lines are pre-discharged to a low level.

Description

technical field [0001] The present application relates to the technical field of semiconductors, in particular to a static random access memory (SRAM) unit and related devices. Background technique [0002] Static random access memory (SRAM) is a storage device with static access function, which can save the data stored in it without refreshing the circuit, and is widely used in the design of digital and various electronic circuit products. When performing read / write operations on SRAM, it is necessary to charge and discharge the bit lines of the SRAM. Therefore, frequent read / write operations on the SRAM will result in a large power consumption of the SRAM, which in turn limits the processor that needs to frequently access the SRAM. processing speed. [0003] Take the storage unit in the SRAM as an example to read data from the traditional 6T-SRAM unit, such as figure 1 As shown, the 6T-SRAM unit includes 6 transistors, namely transistors M1 - M6 . When the data stored i...

AI Technical Summary

Problems solved by technology

When performing read / write operations on SRAM, it is necessary to charge and discharge the bit lines of the SRAM. Therefore, frequent read / write operations on the SRAM will result in a large power consumption of the SRAM, which in turn limits the processor that needs to frequently access the SRAM. processing speed

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