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Layout interconnection line defect inspection system and inspection method thereof

A defect inspection and interconnection line technology, applied in the layout interconnection line defect inspection system and its inspection field, can solve problems such as troublesome testing, low efficiency, and inaccurate inspection, and achieve the effect of improving inspection efficiency and accuracy

Active Publication Date: 2020-03-17
EDGELESS SEMICON CO LTD OF ZHUHAI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to overcome the technical problems of inaccurate inspection, low efficiency, and troublesome testing of interconnection defects in the prior art, and to provide a layout interconnection defect inspection system and its inspection method

Method used

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  • Layout interconnection line defect inspection system and inspection method thereof
  • Layout interconnection line defect inspection system and inspection method thereof
  • Layout interconnection line defect inspection system and inspection method thereof

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specific Embodiment 1

[0033] Such as figure 2 As shown, a layout interconnection line defect inspection method, the layout is a multi-layer metal interconnection structure, the two adjacent layers of metal are connected by via stacking, and there are bottlenecks in the same layer of metal and via stacking possible, this embodiment finds the area of ​​the metal connection bottleneck from both horizontal (same-layer metal Metal) and vertical (through-hole stack Via) directions, including the following steps:

[0034] S1: Determine network nodes according to inspection targets such as power lines, ground lines, and radio frequency lines;

[0035] S2: According to the network nodes, determine the connection nodes between the metal layers, between the via stacks, and between the metal layers and the via stacks. Specifically, Metaln-1 is connected to Metaln through Vian-1, where n is the metal level, and the network node It can be passed to each connected metal layer in this way, and according to the n...

specific Embodiment 2

[0039] This embodiment has the same layout interconnection line defect inspection system as the specific embodiment 1, and the difference from the specific embodiment 1 is that this embodiment uses the difference in the number of via stacks to obtain the bottleneck area of ​​the via stack.

[0040] Such as Figure 7 As shown, a layout interconnect defect inspection method includes the following steps:

[0041] S1: Determine the network node according to the inspection target power line, ground wire, and radio frequency line;

[0042] S2: Determine the connection nodes between the metal layers of each layer, between the via stacks, and between the metal layers and the via stacks according to the network nodes, and the connection relationship is the same as that of the specific embodiment 1;

[0043] S3: select the metal layer sequentially to zoom out according to the first preset threshold A, and then zoom in to obtain the theoretical metal layer. The specific implementation m...

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Abstract

The invention discloses a layout interconnection line defect inspection system and an inspection method thereof. The layout is of a multi-layer metal interconnection structure, every two adjacent layers of metal are connected in a stacked mode through a through hole, and network nodes are determined according to an inspection target; according to the network nodes, communication nodes among metallayers, among through hole stacks and between the metal layers and the through hole stacks are determined; the metal layers are sequentially selected for operation to obtain theoretical metal layers,and the selected metal layers are compared with the corresponding theoretical metal layers to obtain defect bottlenecks of the metal layers; the through hole stacks are sequentially selected for operation to obtain defect bottlenecks of the through hole stacks. The layout is advantaged in that through connectivity of a layout graph, operation and screening operation are carried out through a set threshold value, the specific area and the shape of the bottleneck defect of stacking of the metal layers and the through holes are obtained, and inspection efficiency and accuracy are improved.

Description

technical field [0001] The invention relates to the technical field of defect inspection of integrated circuit layout design, in particular to a defect inspection system and inspection method for layout interconnection lines. Background technique [0002] With the gradual progress of the semiconductor integrated circuit manufacturing process, the feature size of the transistor is getting smaller and smaller, the integration degree of the circuit per unit area is higher, the metal wiring level is more and more, the interconnection line density is getting higher and higher, and the layout design is getting better and better. As it becomes more and more complicated, it becomes more and more difficult to inspect interconnection defects in the layout. In layout design, it is very necessary to inspect power supply, ground, key signal lines, etc. Interconnection defects will cause short circuit, leakage and product function Failure. According to statistics, more than 70% of the fai...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/54G01R31/52G01R31/58G01R31/70
Inventor 谢育桦王静殷惠萍王聪张永光张亮彭新朝徐以军冯玉明黄穗彪
Owner EDGELESS SEMICON CO LTD OF ZHUHAI
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