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Charge pump circuit for delay-locked loop

A delay-locked loop and charge pump technology, applied in the field of microelectronics, can solve problems affecting the performance characteristics of delay-locked loops, current mismatch, charge sharing, etc.

Pending Publication Date: 2020-04-17
CHONGQING UNIV OF POSTS & TELECOMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In any case, the traditional charge pump circuit has problems such as charge sharing, current mismatch, feedthrough, etc., which directly affect the performance characteristics of the delay-locked loop

Method used

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  • Charge pump circuit for delay-locked loop
  • Charge pump circuit for delay-locked loop
  • Charge pump circuit for delay-locked loop

Examples

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Embodiment

[0023] A charge pump circuit for a delay locked loop such as figure 2 As shown, it includes a charge and discharge current bias circuit 1 and a charge pump core circuit 2; wherein, the signal output of the charge and discharge current bias circuit 1 is connected to the signal input terminal of the charge pump core circuit 2; the charge and discharge The current bias circuit 1 provides a bias signal for the charge pump core circuit 2 .

[0024] The current mirrors of the charge and discharge current bias circuit 1 all adopt a current mirror structure that operates in a linear region MOS transistor as source negative feedback impedance to improve current accuracy; the charge pump core circuit 2 adopts the gate of the NMOS transistor M20 and the PMOS The gate of the transistor M19 is connected and the source of the NMOS transistor M20 is connected to the external ground GND structure to suppress the charge sharing effect between the parasitic capacitance of node A and the capaci...

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PUM

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Abstract

The invention discloses a charge pump circuit for a delay-locked loop. The charge pump circuit comprises a charge-discharge current bias circuit and a charge pump core circuit. The charge-discharge current bias circuit adopts an MOS tube working in a linear region as a source negative feedback impedance structure to improve the current precision. The charge pump core circuit adopts technologies that the gate electrode of an NMOS tube M20 is connected with the gate electrode of a PMOS tube M19, and the source electrode of the NMOS tube M20 is connected with an external ground wire GND structure, the gate electrode of the PMOS tube M21 is connected with the gate electrode of the NMOS tube M22, and the source electrode of the PMOS tube M21 is connected with an external power supply VDD structure and the like to suppress circuit charge sharing effects. The charge / discharge current matching performance of the charge pump is improved by adopting the discharge feedback circuit and the chargefeedback circuit; a PMOS tube M17 and an NMOS tube M18 are respectively adopted to form an MOS capacitor to inhibit the problem of output end jitter caused by feed-through in a charge pump switching stage, so that the charge pump circuit for the delay-locked loop is realized.

Description

technical field [0001] The invention belongs to the technical field of microelectronics, and in particular relates to a charge pump circuit for a delay phase-locked loop. Background technique [0002] With the development of communication and computer technology, the requirements for signal transmission and processing speed are getting higher and higher, so the clock signal required by the system puts forward higher requirements. Delay-locked loops are widely used in system clock signal generation circuits because of their high stability, no jitter accumulation, and low phase noise. As an important module of delay-locked loops, charge pumps directly affect the performance of delay-locked loops. performance, which in turn affects the performance characteristics of the system. [0003] figure 1 It is a traditional charge pump circuit, the PMOS tube M1 constitutes the charging current source, the NMOS tube M4 constitutes the discharging current source, the PMOS tube M2 is the...

Claims

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Application Information

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IPC IPC(8): H03L7/089
CPCH03L7/0891
Inventor 周前能王道明李红娟
Owner CHONGQING UNIV OF POSTS & TELECOMM
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