Stress compensation method for MEMS wafer level packaging
A technology of wafer-level packaging and stress compensation, which is applied in the fields of crafts, measuring devices, and decorative art for producing decorative surface effects, and can solve the problems of low bonding strength, reduced mechanical reliability of bonded packaging, and full temperature stability of devices problems such as stability and large deviation of bonding alignment, etc., to achieve the effect of improving mechanical strength, improving mechanical reliability, and reducing the influence of structural deformation
Active Publication Date: 2020-05-08
BEIJING INST OF AEROSPACE CONTROL DEVICES
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Problems solved by technology
[0004] The technical problem solved by the invention is: to overcome the large deviation of bonding alignment and low bonding strength caused by excessive wafer deflection during the MEMS wafer-level bonding packaging process, and the unbalanced stress will reduce the bonding package. To solve the problems of mechanical reliability and full temperature stability of devices, the present invention provides a stress compensation method for MEMS wafer-level packaging, which uses the mirror symmetry compensation method to balance the stress on both sides of the bonding sheet and reduce the stress of the bonding sheet. flex
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[0030] The present invention will be further elaborated below in conjunction with embodiment.
[0031] A stress compensation method for MEMS wafer-level packaging proposed by the present invention, the bonding package structure includes: a capping layer, a device layer and a substrate layer; the front side of the capping layer contains a cavity structure and is used for Si-SiO 2 Bonded SiO 2 Film layer structure, the back of the capping layer has thermal oxidation SiO that is processed simultaneously with the front 2 The device layer contains the device structure, and the front side of the substrate layer includes the cavity structure, Au film structure, W electrode film structure and SiO 2 Insulation layer structure; Si-SiO is passed between the front of the capping layer and the back of the device layer 2 Direct bonding to form an SOI sheet. After the device structure is processed on the front side of the SOI sheet device layer, it is bonded with the front side of the subs...
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Abstract
The invention discloses a stress compensation method for MEMS wafer-level packaging, and the method comprises the steps: processing a silicon dioxide pattern structure which is completely in mirror symmetry with the front surface of a silicon wafer at the back surface of the silicon wafer when the silicon wafer at a sealing cap layer is processed; bonding the sealing cap layer silicon wafer and the device layer silicon wafer together through Si-SiO2 to form an SOI wafer, and then completing processing of the device layer; processing a SiO2 / W / SiO2 / Au film layer structure which is completely inmirror symmetry with the front surface on the back surface of the substrate layer silicon wafer when the substrate layer silicon wafer is processed; and finally, bonding the SOI wafer processed by theback mirror image film layer structure with the substrate layer silicon wafer to finish packaging. According to the invention, a mirror symmetry compensation method is utilized to balance the film stress on the two sides of the wafer to be bonded, and the problems of large bonding alignment deviation and low bonding strength caused by excessive wafer deflection in the MEMS wafer-level bonding packaging process are solved.
Description
technical field [0001] The invention relates to a stress compensation method for MEMS wafer-level packaging, which belongs to the field of micro-electromechanical system (MEMS) micromachining. The invention relates to a method for reducing the deflection of a sheet to be bonded by using a mirror image compensation method. Background technique [0002] The fundamental purpose of MEMS device packaging is to serve a group of components with specific functions with the smallest size and weight, the lowest price and the simplest structure possible. MEMS wafer-level packaging technology refers to the realization of mechanical and electrical connections between different layers of MEMS chips by means of silicon wafers as a unit before the separation of a single MEMS chip, through wafer bonding or thin film deposition, and the realization of wafer-level packaging. The independent sealing technology of each MEMS chip microstructure. Compared with device-level packaging, wafer-level...
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IPC IPC(8): B81C1/00B81C3/00B81B7/00B81B7/02
CPCB81C1/00325B81C1/00301B81B7/007B81B7/02B81B7/0006B81C3/001Y02P70/50
Inventor 崔尉刘福民邱飞燕梁德春刘宇张树伟杨静张乐民吴浩越马骁
Owner BEIJING INST OF AEROSPACE CONTROL DEVICES