SEC verification method and device for FPGA configuration memory

Abstract

The invention discloses an SEC verification method for an FPGA configuration memory. The SEC verification method comprises the steps of: acquiring and storing a reference ECC verification code; performing ECC check on data in an FPGA configuration memory frame by frame according to the reference ECC check code and modifying error data; and carrying out CRC on the data in the FPGA configuration memory and carrying out data resetting on all frames in the configuration memory when an error occurs. The invention further discloses an SEC verification device for the FPGA configuration memory, whichcomprises a verification code storage module, an SEC verification module, a correction module, a configuration module and an off-chip memory, and is used for executing the SEC verification method. According to the SEC verification method and the SEC verification device, ECC verification and CRC verification are used for carrying out detection and error correction on the data in the FPGA configuration memory when the FPGA chip normally works, and the two verification modes act together, so that the working correctness and stability of the FPGA chip are improved.

Description

technical field [0001] The invention belongs to the technical field of FPGA configuration memory, in particular to an SEC verification method and device for FPGA configuration memory. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Gate Array) configuration memory is distributed throughout the FPGA chip and is the largest number of storage units inside the chip. The data in it controls configurable logic resources such as wiring resources and look-up tables, which determine behavior of user circuits. In the process of configuring the FPGA chip, it will be divided into multiple addresses according to the distribution position of each storage unit of the configuration memory, and each address stores data of a fixed length. After the FPGA configuration is completed and enters the normal working state, due to various factors, the data in the internal configuration memory of the chip may be wrong, causing the chip to fail to work normally. ...

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Problems solved by technology

[0003] Disclosed a kind of soft error detection method in the prior art, is used for checking and correcting the error in the FPGA configuration memory, its implementation method is to carry out CRC (CyclicRedundancy Check, cyclic redundancy check) after reading all data in the FPGA configuration memory I check), if an error is found, restart the configuration, write all the configuration data saved in the off-chip memory into the FPGA configuration memory again, but restart the configuration only in MSPI (Master Serial Peripheral Interface, master serial peripheral interface) configuration mode Errors in the configuration data cannot be corrected in other configuration modes, and the error detection rate and modification rate will be limited by the disadvantages of the verification method itself

[0004] Another existing soft error buffering method is used to check and correct the errors in the FPGA configuration memory. In the process of data correction, rewriting the corrected frame of configuration data into the FPGA configuration memory is achieved by controlling the start-up configuration module through multiple modules and executing the command to write configuration data, and the configuration module needs to be generated Recognizable bit stream data, complex operation

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