A high-speed sampling circuit for 8t pixel and its control method

Abstract

A high-speed sampling circuit for an 8T pixel and a control method thereof, the sampling circuit includes an operational amplifier, an external test photoelectric signal strobe switch, an external test reset signal strobe switch, a column sampling switch, an adjustable sampling capacitor control switch, Adjustable feedback capacitor control switch, buffer switch, output sampling reset control switch, output sampling signal control switch, output sampling reset control switch, output sampling signal control switch, sampling capacitor, feedback capacitor and output sampling capacitor. Different from the traditional correlation double sampling circuit, the present invention improves the output rate of the readout circuit through the continuous flow sampling circuit, has external testability design, offset removal design, low noise timing design and high-speed output sampling design, and improves the data processing speed .

Description

technical field [0001] The invention belongs to the field of image sensors, and in particular relates to a high-speed sampling circuit for an 8T pixel and a control method thereof. Background technique [0002] The image sensor is the core of the modern electronic imaging system, and the image sensor is mainly implemented based on two processes, CMOS process and charge-coupled device (CCD) process. CMOS image sensor technology has achieved rapid development in recent years due to its advantages of high integration, small size, and low power consumption. The speed and accuracy of the CMOS image sensor readout circuit determine the frame rate, dynamic range, and MTF (modulation transfer function) of the sensor. Therefore, its design directly affects the function and performance of the image sensor. There are many noise sources in the pixel of the image sensor. In order to improve the signal-to-noise ratio, dynamic range and consistency of the pixel array of the system, the ou...

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Problems solved by technology

figure 1 Shown is the PGA circuit applied to 4TAPS pixel sampling. Under a certain timing design, the sampled reset signal and photoelectric signal can be correlated, which can effectively reduce the reset noise of the RST tube. For smaller area array image sensors , such an exposure method and sampling circuit are very reasonable, but for large-scale or even ultra-large-scale area arrays, due to the poor charge storage ability of FD points, it is not suitable for global exposure mode

[0003] like Figure 4 The 8T APS pixel circuit is shown, because the capacitors C1 and C2 for storing charges are added inside the pixel, so that the pixel has a space storage capacity for the sampling signal. In the global exposure mode, the capacitors C1 and C2 respectively store The reset signal and the photoelectric signal can be stored under the same conditions, so that the error caused by the leakage of the capacitor can be ignored, so Figure 4 The 8T APS pixel circuit shown is more suitable for the design of large area array image sensor in the global exposure mode, but the large area array design also faces the problem of large amount of data processed by the system, and the slow processing speed leads to low frame rate. figure 1 Among them, the same correlated double sampling circuit design can achieve low-noise sampling effect, but the speed has not changed.

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