Clock data recovery circuit

Abstract

The invention discloses a clock data recovery circuit. The circuit comprises at least one phase discriminator, a phase difference generation sub-circuit, a charging pump and a first recovery sub-circuit, wherein the phase discriminators are in one-to-one correspondence with the links; the phase discriminator generates a phase difference signal and a data signal according to an input signal from acorresponding link of the phase discriminator and a recovery clock signal from the first recovery sub-circuit; the phase difference generation sub-circuit generates a final phase difference signal according to the phase difference signal input by each phase discriminator; the charging pump generates a voltage difference signal according to the final phase difference signal, and the first recoverysub-circuit is used for generating the recovery clock signal according to the voltage difference signal and feeding back the recovery clock signal to the phase discriminator. According to the scheme provided by the embodiment of the invention, a plurality of phase difference signals are integrated into one phase difference signal, only one path of clock is recovered, and the power consumption is greatly reduced by reducing the clock.

Description

technical field [0001] This paper relates to electronic technology, especially a clock data recovery circuit. Background technique [0002] At present, the high-speed interface of data transmission adopts the serial interface (SerDes), the main reason is that it can very well solve the problems of data skew (Skew) and interference (Crosstalk) encountered in the parallel interface. And in theory, the serial interface is easier to increase the upper limit of the speed, as long as the receiving end can better recover the clock and data of the sending end. The circuit that realizes this function is Clock and Data Recovery (CDR for short), so the quality of the CDR design directly affects the performance of the interface, and is a very important part of the entire SerDes interface. [0003] A multi-lane SerDes interface generally adopts a method in which each lane is individually equipped with a CDR circuit, that is, each lane (lane) restores its own clock and data. The recover...

AI Technical Summary

Problems solved by technology

[0006] The Clock and data recovered between Lane and Lane will have skew, which will easily cause the subsequent logic circuit to identify data errors, resulting in communication failure;

[0007] Larger circuit area, larger power consumption and poorer performance, unstable

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