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Semiconductor product and fabrication process

A semiconductor and process technology, applied in the field of manufacturing semiconductor products, which can solve problems such as damage to the gate structure

Pending Publication Date: 2020-07-31
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, aluminum is a soft metal and vertical stresses formed on the aluminum above transistor gate structures during fabrication or packaging can damage the gate structures

Method used

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  • Semiconductor product and fabrication process
  • Semiconductor product and fabrication process
  • Semiconductor product and fabrication process

Examples

Experimental program
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Embodiment Construction

[0010] In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and claims, the terms "comprising", "comprising", "having", "having", "with" or variations thereof are intended to be inclusive in a manner similar to the term "comprising", and should therefore be construed to mean "including but not limited to". For purposes of illustration, several examples are described below with reference to example applications. Various specific details, relationships, and methods are set forth to provide an understanding of the concepts disclosed. The concepts disclosed may be practiced without one or more of the specific details or by other means. The disclosed concepts are not limited by the order of acts or events illustrated, as some acts may occur in different orders and / or concurrently with other acts or events. Moreover, not all illustrated acts or events may be required to...

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Abstract

Processes(100) for fabricating a semiconductor product(200) and for forming a patterned stack with an aluminum layer(218) and a tungsten layer(216), include forming(104) a first dielectric layer(212)on a gate structure(204) and on first and second regions(208, 210) of a substrate(202), forming(108) a diffusion barrier layer(214) on the first dielectric layer(212), forming(110) a tungsten layer(216) on the diffusion barrier layer(214), forming(112) an aluminum layer(218) on the tungsten layer(216), forming(114) a hard mask layer(220) on the aluminum layer(218), forming(116) a patterned resistmask layer(222) which covers the hard mask layer(220) above the first region(208) and exposes the hard mask layer(220) above the second region(210), dry etching(118, 120) the hard mask layer(220) andthe aluminum layer(218) above the second region(210) using the patterned resist mask layer(222), removing(122) the resist mask layer(222), and dry etching(124) the tungsten layer(216) using the hard mask layer(220) to expose the first dielectric layer(212) above the second region(210).

Description

technical field [0001] The present invention is directed to semiconductor devices, and in particular to fabrication techniques for producing semiconductor products. Background technique [0002] Metallization structures are used to conduct electrical current and provide electrical connections to transistor terminals and other semiconductor devices in discrete semiconductor products and integrated circuits. The thick aluminum metal interconnect structure formed on the front metal dielectric can accommodate high current levels for power switching applications and the like. However, aluminum is a soft metal and vertical stress formed on the aluminum over transistor gate structures during fabrication or packaging can damage the gate structures. Contents of the invention [0003] The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention and is intend...

Claims

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Application Information

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IPC IPC(8): H01L21/768
CPCH01L23/53266H01L23/53223H01L21/76885H01L21/76847H01L21/28556H01L21/32136
Inventor 陈亚平杨红阿巴斯·阿里左超赛特拉曼·西达尔刘运龙
Owner TEXAS INSTR INC
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