High-erasing-speed semi-floating-gate memory and preparation method thereof

Abstract

The invention belongs to the technical field of integrated circuit memories, and particularly relates to a high-erasing-speed semi-floating-gate memory and a preparation method thereof. The semi-floating-gate memory comprises a silicon-containing semiconductor substrate having a first doping type, a semi-floating-gate well region which has a second doping type, and a U-shaped groove which penetrates through the semi-floating-gate well region, wherein the bottom of the U-shaped groove is located at the lower boundary of the semi-floating-gate well region; a first gate dielectric covers the surface of the U-shaped groove, and an opening is formed in the semi-floating-gate well region; a floating gate covers the first gate dielectric, and a metal silicide is formed in the semi-floating-gate well region below the opening; a second gate dielectric layer wraps the floating gate, and a control gate covers the second gate dielectric layer; gate side walls are positioned on the two sides of a first gate stack and a second gate stack; and a source region and a drain region have a second doping type and are positioned on two sides of the first gate stack and the second gate stack. According to the invention, the erasing speed of the memory can be increased, the contact resistance of the source electrode of a tunneling transistor is obviously reduced, the driving current of the tunneling transistor is increased, and the erasing speed of the memory is further increased.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit memory, and in particular relates to a high erasing and writing speed semi-floating gate memory and a preparation method thereof. Background technique [0002] At present, the DRAM devices used in integrated circuit chips are mainly 1T1C structures, that is, a transistor is connected in series with a capacitor, and the capacitor is charged and discharged through the switching of the transistor, thereby realizing the conversion between 0 and 1 of the DRAM device. As the device size becomes smaller and smaller, DRAM devices used in integrated circuit chips are facing more and more problems. For example, DRAM devices require 64ms refresh time, so the capacitance value of the capacitor must be kept above a certain value to ensure a long enough time. However, with the shrinking of the feature size of integrated circuits, the manufacture of large capacitors has become more and more difficult,...

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Problems solved by technology

In addition, as the size of the transistor continues to shrink, the opening where the source of the tunneling transistor is also shrinking, which causes the contact resistance at the opening to increase, thereby reducing the speed of the tunneling transistor

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