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a computing architecture

A computing architecture and computing array technology, applied in the field of computing architecture, can solve problems such as frequent CacheMiss, low Cache utilization, and restricting computing performance, so as to reduce performance bottlenecks, reduce CacheMiss, and improve flexibility.

Active Publication Date: 2022-04-05
XI AN JIAOTONG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Specifically, when this type of computing library handles large-scale equation system solving and matrix operations, it will inevitably have the problems of frequent Cache Miss and low computing efficiency.
At this time, the extremely low Cache utilization and limited memory bandwidth become the main bottleneck restricting performance, seriously restricting the overall computing performance

Method used

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Embodiment Construction

[0033] In one embodiment, such as figure 1 As shown, a computing architecture is disclosed, including: off-chip memory, on-chip cache unit, transmitting unit, pre-reorganization network, post-reorganization network, main computing array, data dependency controller and global scheduler; wherein,

[0034] An off-chip memory for storing all large-scale data in a block format, wherein the large-scale data is divided into multiple blocks of equal size;

[0035] The on-chip cache unit is used to store part of the data of the block to be calculated and the dependent data required for the calculation;

[0036] The transmitting unit is used to read the data of the corresponding block from the on-chip cache unit and send it to the pre-reassembly network according to the order specified by the scheduling algorithm;

[0037] The main calculation array is used to complete the calculation of the data of the main block;

[0038] Pre-reorganization network, which is used to perform arbitrar...

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Abstract

A computing architecture comprising: off-chip memory, on-chip cache unit, prefetch unit, global scheduler, issue unit, pre-reorganization network, post-reorganization network, main computing array, write-back cache unit, data dependency controller, and auxiliary computing array. This architecture reads the data blocks into the on-chip cache by prefetching, and calculates according to the data blocks; in the calculation process of the blocks, the block exchange network is used to reorganize the data structure, and the data dependency module is set to process different blocks data dependencies that may exist between them. The computing architecture can improve data utilization and data processing flexibility, thereby reducing cache misses and memory bandwidth pressure.

Description

technical field [0001] The disclosure belongs to the technical field of processing large-scale data, and in particular relates to a computing architecture. Background technique [0002] Solving large-scale linear equations and matrix operations is one of the most critical operations in modern scientific computing and engineering computing. At present, such operations mainly rely on high-performance linear algebra libraries, such as CUBLAS on GPU platforms, and computing libraries such as Linear Algebra Package (LAPACK) and Intel Math Kernel Library (MKL) on CPU platforms. This type of computing library generally adopts matrix inversion and equation group solving algorithms based on LU decomposition, and uses the Single Instruction Multiple Data (SIMD) style of high-parallel computing units to achieve maximum parallelization of data processing. . However, for large-scale problems, the computing data cannot be completely stored in the on-chip cache (such as multi-level cache...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/78
CPCG06F15/7867G06F15/781G06F12/0813G06F12/0862G06F2212/454G06F12/0207G06F2212/1024G06F2212/1048G06F12/0879G06F12/0804G06F9/3555G06F9/3838G06F9/3887G06F2212/1021
Inventor 夏天任鹏举赵浩然李泽华赵文哲郑南宁
Owner XI AN JIAOTONG UNIV
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