Manufacturing method of silicon-on-insulator PMOS device

Abstract

The invention relates to a manufacturing method of a silicon-on-insulator PMOS device. The method comprises the steps that a base is acquired, wherein the base comprises a substrate, a buried oxide layer on the substrate and a semiconductor layer on the buried oxide layer, an N well, a source electrode region and a drain electrode region are formed in the semiconductor layer, and a gate electrodeis formed on the semiconductor layer; a dielectric layer covering the semiconductor layer and the gate electrode is formed; a plurality of through holes are formed in the dielectric layer, a metal connecting line layer is formed on the dielectric layer, and the source region, the drain region and the gate electrode are led out by the metal connecting line layer through conductive media filled in the through holes; a passivation layer is formed on the metal connecting line layer, the passivation layer is patterned through photoetching and etching, and etching is dry etching; and then a heat treatment process is carried out, wherein the process temperature of the heat treatment is greater than 420 DEG C. By increasing the process temperature of heat treatment, the back gate turn-on voltage of the PMOS tube is effectively increased, and the problem of excessive electric leakage of the PMOS device in the traditional process is solved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to a method for manufacturing a silicon-on-insulator PMOS device. Background technique [0002] Compared with ordinary bulk silicon devices, SOI (Silicon-On-Insulator, silicon on insulator) devices have a series of advantages such as good isolation effect, no latch-up effect, good radiation resistance effect, small parasitic capacitance, and small chip design area. [0003] Generally, SOI includes 3 levels: substrate (handle wafer), buried oxide layer (BOX) on the substrate, and semiconductor layer (SOI) on the buried oxide layer. For PMOS transistors on SOI substrates, viewing from the bottom up There is a parasitic device: the gate of the parasitic device is the Si substrate, the buried oxide layer is the gate oxide of the parasitic device, the source region and the drain region of the parasitic device are P+ in the semiconductor layer, and the N well in ...

AI Technical Summary

Problems solved by technology

When the turn-on voltage of the back gate is small, there will be a problem of excessive leakage of the device (when the substrate has some unknown induced charges, it is easy to form a parasitic channel near the BOX on the top layer of silicon, resulting in leakage of the device on the front, resulting in circuit effective)

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