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Multilayer organic substrate and manufacturing method thereof

A technology of organic substrates and manufacturing methods, which is applied in the fields of multilayer circuit manufacturing, removal of conductive materials by chemical/electrolytic methods, and printed circuit manufacturing. Suitable for problems such as extremely high layers and high thickness requirements of MLO substrates, high cost, etc., to achieve the effect of improving product competitiveness, excellent electrical performance, and lowering the manufacturing threshold

Active Publication Date: 2020-08-25
上海泽丰半导体科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the extremely high line density requirements for MLO docking and chip layer C4, the subtractive process used in traditional PCB / BGA can no longer be produced, and even the mSAP process commonly used in Substrate is difficult to meet the requirements. The latest technical requirements can only be used in Japan. Universiade Ajinomoto’s ABF film’s full-additive SAP process, this electroplating process is mostly used for packaging substrates in high-performance computing fields such as high-end CPU / GPU due to its high cost, technically limit line width / line spacing ( 15 / 15um), the production of MLO based on the existing process requires more than 10 lines, pressing and drilling processes, the process is complex, the cost is high, the delivery period is long, and the technology has reached a bottleneck, and it is difficult to continue to advance
[0004] Embedded circuit technology originates from the ancient damascene process (damascene process), which is used in high-density additive / semi-additive wiring in the field of semiconductor packaging. It is suitable for making a single high-density wiring layer of packaging substrates. It is generally used In the field of thin substrates with a small number of layers, the number of increments generally does not exceed 3 times. The more layers, the higher the cost compared with the traditional double-sided layer buildup process. The embedded circuit process still accounts for a relatively low proportion in the current packaging substrate field. , the single buried line process cannot be suitable for MLO substrates with extremely high layer count and high thickness requirements

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  • Multilayer organic substrate and manufacturing method thereof
  • Multilayer organic substrate and manufacturing method thereof
  • Multilayer organic substrate and manufacturing method thereof

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Embodiment Construction

[0060] In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the specific embodiments of the present invention will be described below with reference to the drawings. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative work, other drawings can be obtained based on these drawings and obtained Other embodiments.

[0061] In order to make the drawings concise, the drawings only schematically show the parts related to the present invention, and they do not represent the actual structure of the product. In addition, in order to make the drawings concise and easy to understand, in some drawings, only one of the components with the same structure or function is schematically shown, or only one of them is marked. In this article, "a" not only means "only this one", but can also mean "more than one".

[0062] An embo...

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Abstract

The invention belongs to the technical field of semiconductor testing, and provides a multilayer organic substrate and a manufacturing method. The method comprises the steps of manufacturing a probe implantation layer with a first precision circuit on a bearing plate through an addition method / semi-addition method; manufacturing a functional combination layer with a second precision circuit on theprobe implantation layer by an addition method / semi-addition method, wherein the circuit precision requirement of the second precision circuit is lower than that of the first precision circuit; manufacturing a core combination layer capable of quickly adding layers by combining a dielectric layer and a conductor layer which are manufactured in parallel, and covering the core combination layer onthe function combination layer; and manufacturing a fan-out circuit combination layer and a BGA PAD layer for transferring load board on the core combination layer by the addition method / semi-additionmethod so as to form the multilayer organic substrate. The manufacturing method of the multilayer organic substrate is low in cost and short in manufacturing period, so that the C4 Pad minimum spacing of the multilayer organic substrate is reduced, the wiring density of the probe implantation layer is improved, and meanwhile, the C4 Pad surface can obtain super-flatness.

Description

Technical field [0001] The invention relates to the field of semiconductor testing, in particular to a multilayer organic substrate and a manufacturing method. Background technique [0002] MLO is the abbreviation of Multi layered Organic substrate. Chinese means multi-layer organic substrate. It is used to test uncut wafers with vertical probe cards; the size of the probes implanted on the MLO needs to match the wafer under test Contact (C4 Pad), so this requires the MLO substrate to have a high-precision circuit layer (C4 Side), and the needle implantation and testing require the substrate to have high rigidity and strength, usually by increasing the total board thickness to meet the requirements, wafer testing The probe is required to have good coplanarity, which requires the MLO substrate on which the probe is implanted to have good surface flatness. [0003] The existing manufacturing method of the MLO multilayer organic substrate is the traditional core layer build-up proces...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05K3/46H05K3/06H05K3/00H05K3/42H05K3/28H05K1/02H05K1/11
CPCH05K1/0298H05K1/115H05K3/0026H05K3/0047H05K3/0094H05K3/06H05K3/282H05K3/423H05K3/4644
Inventor 陶克文罗雄科袁凯华
Owner 上海泽丰半导体科技有限公司
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