Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor device and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electric solid devices, electrical components, etc., can solve the problems of internal stress that cannot effectively control the cost of device manufacturing

Inactive Publication Date: 2020-10-20
YANGTZE MEMORY TECH CO LTD
View PDF6 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to control the manufacturing cost of the device and the internal stress of the device, the common source of the array is usually filled with tungsten and polysilicon (poly). However, as the number of stacked layers of the 3D memory device increases, the use of tungsten and polysilicon can not effectively control the device. cost and internal stress of the device

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0057] Such as figure 1 As shown, the embodiment of the present application provides a semiconductor device 1, such as a 3D NAND storage device; the semiconductor device 1 includes a substrate 2, a stack layer 3 located on the substrate 2, and a stacked The layer 3 has gate slits 4 with sidewalls and bottoms, and an array common source 5 formed in the gate slits 4 .

[0058] The substrate 2 is a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator, Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator) and the like. Of course, the substrate 2 can also be a substrate 2 including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or it can also be a stacked structure, such as Si / SiGe, etc., and can also include other epitaxial structures, such as SGOI (Silicon germanium on insulator) and so on.

[0059] The stacked layer 3 can be formed by a single stack (Sing...

Embodiment 2

[0069] Such as figure 2 As shown, the present application also provides a semiconductor device 1, which is different from the first embodiment above in that the stress adjustment layer 14 includes a first filling layer 19 and a second filling layer 20 sequentially arranged in the gate gap 4; The material of a filling layer 19 includes any one of spin-on carbon and silicon dioxide, and the material of the second filling layer 20 is polysilicon.

[0070] Specifically, the material of the first filling layer 19 is spin-pair carbon, and the material of the second filling layer 20 is polysilicon; or, the material of the first filling layer 19 is silicon dioxide, and the material of the second filling layer 20 is polysilicon. The filling ratio of the first filling layer 19 and the second filling layer 20 can be adjusted according to the requirement of stress.

[0071] It should be noted that, in other implementation manners, the material of the first filling layer and the material...

Embodiment 3

[0074] Such as figure 2 As shown, the present application also provides a semiconductor device, which is different from the above-mentioned second embodiment in that the material of the second filling layer 20 includes one of spin-pair carbon and silicon dioxide that is different from the material of the first filling layer 19 kind.

[0075] Specifically, the material of the first filling layer 19 is spin-to-carbon, and the material of the second filling layer 20 is silicon dioxide; or, the material of the first filling layer 19 is silicon dioxide, and the material of the second filling layer 20 is spin on carbon.

[0076]In this embodiment, since the cost of spin-to-carbon and silicon dioxide is lower than that of polysilicon, and the stress coefficient is smaller than that of polysilicon, spin-to-carbon and silicon dioxide are used to replace all polysilicon as the array common source 5 The stress adjustment layer 14 can further effectively reduce the manufacturing cost a...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a stacking layer formed on the substrate, a gate gap penetrating through the stacking layer in the direction perpendicular to the substrate, and an array common source formed in the gate gap. The stacking layer comprises a plurality of gate conductor layers and interlayer insulating layers which are stacked alternately. The array common source electrode comprises source electrode conducting layers located on the side wall and the bottom of the grid electrode gap, astress adjusting layer located in the grid electrode gap and surrounded by the source electrode conducting layers, and a source electrode connecting part located in the grid electrode gap, located onthe stress adjusting layer and electrically connected with the source electrode conducting layers. According to the invention, the stress adjusting layer is made of a material with low cost and smallstress coefficient to fill the array common source, so that the manufacturing cost of the device and the internal stress of the device can be effectively controlled.

Description

technical field [0001] The present application relates to the technical field of semiconductor devices and manufacturing thereof, and in particular to a semiconductor device and a manufacturing method thereof. Background technique [0002] NAND storage devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. Planar NAND devices are close to the limit of practical expansion. In order to further increase storage capacity and reduce storage cost per bit, 3D NAND storage devices are proposed. In the structure of 3D NAND storage devices, the method of vertically stacking multi-layer gates is adopted. The central area of ​​the stacked layer is an array storage area, and the edge area is a stepped structure. The array storage area is used to form a string of memory cells. The conductive layer in the stacked layer As the gate line of each layer of memory cells, the gate line is drawn out thr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/1157H01L27/11582H10B43/35H10B43/27
CPCH10B43/35H10B43/27
Inventor 陆聪郭芳芳李伟卢绍祥曾森茂吴振国轩攀登
Owner YANGTZE MEMORY TECH CO LTD