Manufacturing method of deep trench isolation grid structure

Abstract

The invention provides a CMOS image sensor, a pixel structure of the CMOS image sensor and a manufacturing method of a deep trench isolation grid structure in the pixel structure. The manufacturing method of the deep trench isolation grid structure specifically comprises the following steps: providing a stacking layer, wherein a silicon epitaxial layer is arranged at the top of the stacking layer;forming a plurality of grid-shaped deep grooves in the silicon epitaxial layer; sequentially depositing a first isolation layer and a second isolation layer on the side wall and the bottom in each deep groove; and depositing a third isolation layer filling each deep trench on the upper surface of the second isolation layer, so that the first isolation layer, the second isolation layer and the third isolation layer in the plurality of deep trenches form a multi-isolation grid. According to the deep trench isolation grid structure formed by the manufacturing method provided by the invention, the electronic crosstalk between adjacent grids can be effectively reduced, so that the device performance of the CMOS image sensor comprising the deep trench isolation grid structure and the pixel structure of the CMOS image sensor can be effectively improved.

Description

technical field [0001] The invention relates to the field of semiconductor devices and its manufacture, in particular to a CMOS image sensor and its pixel structure, and a method for manufacturing the deep trench isolation grid structure therein. Background technique [0002] In the field of semiconductor technology, a stacked CMOS image sensor (Ultra-Thin Stacked CMOS ImageSensor, UTS CIS) is formed by bonding a separately manufactured logic wafer and pixel wafer through a bonding process. Since the logic wafer and the pixel wafer are manufactured separately, the manufacturing process is flexible and low in cost. Another advantage of this process is that the logic device and the pixel device do not affect each other, and the performance can be maximized to a higher degree. Stacked CIS usually includes two silicon chips and one logic wafer, whose main function is to provide logic function circuits, sequential circuits, storage units, etc. of CIS. Another pixel wafer, its ma...

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Problems solved by technology

[0006] The aggravation of electronic crosstalk caused by the continuous reduction of the size of semiconductor devices can no longer be alleviated by the formation of high dielectric constant films and deep trench isolation of silicon oxide in the prior art.

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