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Polycrystalline self-doped smooth top gate JFET device and manufacturing method thereof

A self-doping and smoothing technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as difficulties for designers, improve the ability to accurately control threshold voltage, and improve device consistency.

Pending Publication Date: 2020-11-13
CHONGQING ZHONGKE YUXIN ELECTRONICS +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For a single active component in a bipolar process, the designer hopes that the characteristics of the device are optimal in all aspects. The JFET tube has a series of advantages such as high input impedance and low bias current, but with the bipolar process With the continuous development of integration technology, the disadvantages displayed are becoming more and more obvious, and there are more and more challenges in terms of withstand voltage, threshold, input impedance, consistency, etc. Therefore, comprehensive consideration of various factors has become a very difficult task for designers. question

Method used

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  • Polycrystalline self-doped smooth top gate JFET device and manufacturing method thereof
  • Polycrystalline self-doped smooth top gate JFET device and manufacturing method thereof
  • Polycrystalline self-doped smooth top gate JFET device and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0078] see Figure 1 to Figure 9 , a polycrystalline self-doped smooth top-gate JFET device, comprising a P-type substrate 100, a P-type buried layer 101, an N-type epitaxial layer 102, a P-type isolation penetration region 103, a field oxygen layer 104, and a pre-oxidation layer 105 , P-type channel region 106, P-type heavily doped source and drain region 107, polycrystalline gate region 108, N-type gate diffusion region 109, TEOS (orthoethyl silicate) metal pre-dielectric layer 110, source and drain first layer metal 111 and gate first layer metal 112 .

[0079] A P-type buried layer 101 is deposited on both ends of the upper surface of the P-type substrate 100 .

[0080] The materials of the P-type substrate 100 and the N-type epitaxial layer 103 include bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0081] The N-type epitaxial layer 102 covers the P-type substrate 100 .

[0082] Both ends of the N-type epitaxial layer 102 are i...

Embodiment 2

[0108] A polycrystalline self-doped smooth top-gate JFET device, comprising an N-type substrate 100, an N-type buried layer 101, a P-type epitaxial layer 102, an N-type isolation penetration region 103, a field oxygen layer 104, a pre-oxidation layer 105, N-type channel region 106, N-type heavily doped source and drain regions 107, polycrystalline gate region 108, P-type gate diffusion region 109, TEOS metal front dielectric layer 110, source and drain first layer metal 111 and gate first layer metal 112 .

[0109] An N-type buried layer 101 is deposited on both ends of the upper surface of the N-type substrate 100 .

[0110] The materials of the N-type substrate 100 and the P-type epitaxial layer 103 include bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0111] The P-type epitaxial layer 102 covers the N-type substrate 100 .

[0112] Both ends of the P-type epitaxial layer 102 are in contact with the N-type buried layer 101 .

[0...

Embodiment 3

[0138] Such as figure 1 As shown, a polycrystalline self-doped smooth top-gate JFET device includes a P-type substrate 100, a P-type buried layer 101, an N-type epitaxial layer 102, a P-type isolation penetration region 103, a P-type channel region 106, P-type heavily doped source-drain region 107, polycrystalline gate region 108, N-type gate diffusion region 109, pre-oxidation layer 105, field oxygen layer 104, TEOS metal pre-dielectric layer 110, source-drain first layer metal 111, gate Pole first layer metal 102.

[0139] The P-type buried layer 101 is located at both ends of the upper surface of the P-type substrate 100 .

[0140] The N-type epitaxial layer 102 is located on the P-type substrate 100 , and the N-type epitaxial layer 102 is in contact with the P-type substrate 100 and the P-type buried layer 101 .

[0141] The P-type isolation penetration region 103 is in contact with both ends of the N-type epitaxial layer 102 , and the bottom of the P-type isolation pene...

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Abstract

The invention discloses a polycrystalline self-doped smooth top gate JFET device and a manufacturing method thereof. The device comprises a P-type substrate 100, a P-type buried layer 101, an N-type epitaxial layer 102, a P-type isolation penetration region 103, a field oxide layer 104, a pre-oxide layer 105, a P-type channel region 106, a P-type heavily doped source-drain region 107, a polycrystalline gate region 108, an N-type gate diffusion region 109, a TEOS metal front dielectric layer 110, a source-drain electrode first layer metal 111 and a gate electrode first layer metal 112. The manufacturing method comprises the following steps: 1) injecting a first conductive type buried layer; and 2) growing a second conductive type epitaxial layer; 3) injecting a first conductive type isolation penetration region; 4) growing a field oxide layer; 5) injecting a first conductive type channel region; 6) injecting the heavily doped source-drain region of the first conductive type; 7) forminga polycrystalline gate region; 8) etching a second conductive type gate diffusion region; and 9) depositing a TEOS metal front dielectric layer, and forming source and drain electrode first layer metal and gate electrode first layer metal. The device can control the magnitude of the input impedance and threshold voltage more accurately.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a polycrystalline self-doped smooth top-gate JFET device and a manufacturing method thereof. Background technique [0002] Due to the late start of domestic technology, technology, and research and development, there are very few involved in advanced modern intelligence and other fields. The domestic modern bipolar analog technology marked by high frequency, high pressure and high precision is still in the stage of research and development and trial production. High-end products are basically monopolized by foreign countries, and there is a certain gap between them and foreign products in general. This cannot be solved in a short period of time, but according to the country's current situation of vigorously developing the semiconductor industry and the premise that the domestic economy has made great progress, the strategy will be steady and steady, and it will catch up st...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/10H01L29/423H01L29/808H01L21/28H01L21/337
CPCH01L29/808H01L29/66901H01L29/1066H01L29/1058H01L29/42316H01L29/401
Inventor 刘建税国华林涛欧红旗冯志成阚玲刘青朱坤峰黄磊王飞张剑乔张培健
Owner CHONGQING ZHONGKE YUXIN ELECTRONICS
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