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Preparation method of flash memory

A technology of flash memory and storage area, which is applied in the field of semiconductors and can solve problems such as difficulty in improving the yield rate of embedded flash memory products

Active Publication Date: 2020-11-20
WUXI CHINA RESOURCES MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] Based on this, it is necessary to provide a preparation method of flash memory for the problem that the yield rate of current embedded flash memory products is difficult to improve

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  • Preparation method of flash memory
  • Preparation method of flash memory
  • Preparation method of flash memory

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Embodiment Construction

[0027] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar improvements without departing from the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of descr...

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Abstract

The invention relates to a preparation method of a flash memory. The method comprises the following steps of: providing a semiconductor substrate, wherein a storage region is defined on the semiconductor substrate, and comprises a plurality of storage unit regions, a plurality of source contact hole regions and a plurality of shallow trench regions; sequentially depositing a first dielectric layerand a first polycrystalline silicon layer on the semiconductor substrate, etching the first polycrystalline silicon layer to remove part of the first polycrystalline silicon layer above the shallow trench region, and reserving the first polycrystalline silicon layer covering the source contact hole regions; and sequentially depositing a second dielectric layer and a second polycrystalline siliconlayer, etching the second polycrystalline silicon layer, the second dielectric layer and the first polycrystalline silicon layer to form a storage unit structure in the storage unit region, and removing the first polycrystalline silicon layer, the second dielectric layer and the second polycrystalline silicon layer above the source contact hole region. According to the invention, the first polycrystalline silicon layer above the source contact hole region is reserved and covered, so that a pit is not formed in the region, and the problem of poor contact between the source region of the memoryunit and the contact plug due to the pit is effectively solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a preparation method of a flash memory. Background technique [0002] With the development and progress of society, the application of semiconductor devices is becoming more and more extensive, and the market share of memory in semiconductor devices is also increasing day by day, but embedded non-volatile memory devices represented by embedded flash memory (E-flash), Due to the complex manufacturing process, high cost and difficulty in improving the yield rate, it limits its own development. [0003] For example, in embedded flash memory products, there are two types of gates, the control gate CG (floating gate FG) and the selection gate SG. During the process, two polysilicon depositions (Poly-dep) and two etchings are required, respectively PC -ET (Poly0-ET) and CG-ET (Poly0 / ONO / Poly1-ET), but due to the overlapping of the etching area during the two etching processes, ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11529H01L27/11531H10B41/35H10B41/41H10B41/42
CPCH10B41/42H10B41/41H10B41/35Y02D10/00
Inventor 马凤麟于绍欣
Owner WUXI CHINA RESOURCES MICROELECTRONICS