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Back metallized semiconductor structure and preparation method thereof

A technology of backside metallization and backside metallization, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as bending and sagging, fragmentation, and wafer fragmentation, and reduce product production. cost, avoid the risk of fragmentation, and improve the effect of product yield

Active Publication Date: 2020-12-01
SIEN QINGDAO INTEGRATED CIRCUITS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003]At present, in the existing power device manufacturing process, due to the continuous reduction of thinning thickness and the accumulated stress in the process, wafer thinning is very easy Fragments occur; in addition, the thinnest wafer thickness can be reduced to less than 100 μm, and when the wafer is stored in the wafer box, it will bend and sag to varying degrees due to its own gravity, and it is very easy to cause vibration of the wafer box, etc. Fragments due to external force
The thinned wafer will also face a huge risk of fragmentation during storage, handling, and subsequent ion implantation, backside metallization and other processes

Method used

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  • Back metallized semiconductor structure and preparation method thereof
  • Back metallized semiconductor structure and preparation method thereof
  • Back metallized semiconductor structure and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0062] see Figure 1 to Figure 8 , the invention provides a method for preparing a backside metallized semiconductor structure, comprising the following steps:

[0063] 1) providing a substrate 101 having a first surface and a second surface oppositely arranged, and a semiconductor device 102 is formed on a side of the substrate 101 close to the first surface;

[0064] 2) forming a trench 103 connecting the second surface and the semiconductor device in the substrate 101;

[0065] 3) forming a back metal layer 104 on the second surface and the surface of the groove 103;

[0066] In step 1), see figure 1 The S1 step and figure 2 A substrate 101 having a first surface and a second surface opposite to each other is provided, and a semiconductor device 102 is formed on a side of the substrate 101 close to the first surface. exist figure 2Among them, the lower surface of the substrate 101 is the first surface, and the upper surface of the substrate 101 is the second surface....

Embodiment 2

[0087] Such as Figure 8 As shown, the present invention also provides a backside metallized semiconductor structure, comprising:

[0088] a substrate 101 having oppositely disposed first and second surfaces;

[0089] a semiconductor device 102, the semiconductor device 102 is formed on a side of the substrate 101 close to the first surface;

[0090] a trench 103, the trench 103 is formed in the substrate 101, and communicates with the second surface and the semiconductor device 102;

[0091] The back metal layer 104 is located on the second surface and the surface of the trench 103 .

[0092] As an example, the semiconductor device 102 includes a power MOS device. The semiconductor device 102 can be formed on the substrate 101 through an existing integrated circuit manufacturing process. Such as Figure 8 As shown, the power MOS device structure includes: a trench gate 102a, an implanted doped region 102b, a bottom dielectric layer 102c, a contact hole plug 102d, a metal...

Embodiment 3

[0096] This embodiment provides a backside metallized semiconductor structure. Compared with Embodiment 2, the difference of this embodiment is that a plurality of semiconductor devices and a plurality of trenches are formed in the substrate, and a plurality of trenches are formed in the substrate. The trenches are in one-to-one correspondence with a plurality of the semiconductor devices.

[0097] In the first embodiment, if Figure 8 As shown, one semiconductor device 102 and three trenches 103 are formed in the substrate 101 . However, in this embodiment, the plurality of trenches in the substrate correspond to a plurality of semiconductor devices one by one, that is, for a single semiconductor device on a wafer, only one trench passes through the plurality of semiconductor devices. The substrate reaches its backside. Specifically, the shape and size of the bottom surface of the groove is the same as that of the semiconductor device, that is, by setting the groove, the bo...

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Abstract

The invention provides a back metallized semiconductor structure and a preparation method thereof, and the preparation method of the back metallized semiconductor structure comprises the following steps: providing a substrate with a first surface and a second surface which are oppositely arranged, and forming a semiconductor device at one side, close to the first surface, of the substrate; forminga groove for communicating the second surface with the semiconductor device in the substrate; and forming a back metal layer on the second surface and the surface of the groove. According to the invention, the groove and the back metal layer are formed on the back surface of the wafer, so that the original back thinning and metallization process is replaced, the fragment risk caused by back thinning is avoided, the product yield is further improved, and the product production cost is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a backside metallized semiconductor structure and a preparation method. Background technique [0002] The application prospect of power MOSFET is very extensive, and it is mainly used in automotive electronics, low-voltage motors, frequency converters, inverters and transformers. In the device structure of power MOSFETs such as insulated gate bipolar transistors (IGBTs), the drain of the device is generally placed on the back of the wafer, and the high power requirements of the power device are met through the design of the drift region structure. Therefore, in the manufacturing process of power devices, the backside thinning process of the wafer has become a key process. [0003] At present, in the existing power device manufacturing process, due to the continuous reduction of thinning thickness and the accumulated stress in the process, the wafer i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L23/482
CPCH01L23/4825H01L21/4846
Inventor 王通李修远
Owner SIEN QINGDAO INTEGRATED CIRCUITS CO LTD
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